Pin Descriptions

Pin No. for

16-pin CSP

Package

Pin No. for

16-pin

TSSOP

Package

Pin Name

I/O

Description

16

1

FoLD

O

Multiplexed output of the Main/Aux programmable or reference dividers

and Main/Aux lock detect. CMOS output. (See Programming Description

2.5)

1

2

OSC

IN

I

PLL reference input which drives both the Main and Aux R counter

inputs. Has about 1.2V input threshold and can be driven from an

external CMOS or TTL logic gate. Typically connected to a TCXO output.

Can be used with an external resonator (See Programming Description

2.5.4).

2

3

OSC

OUT

O

Oscillator output. Used with an external resonator.

3

4

GND

—

Aux PLL ground.

4

5

fin

AUX

I

Aux prescaler input. Small signal input from the VCO.

56

V

CCAUX

—

Aux PLL power supply voltage input. Must be equal to V

range from 2.7V to 3.6V. Bypass capacitors should be placed as close

as possible to this pin and be connected directly to the ground plane.

6

7

CPo

AUX

O

Aux PLL Charge Pump output. Connected to a loop filter for driving the

control input of an external VCO.

78

EN

AUX

I

Powers down the Aux PLL when LOW (N and R counters, prescaler, and

tristates charge pump output). Bringing EN

PLL.

89

EN

MAIN

I

Powers down the Main PLL when LOW (N and R counters, prescaler,

and tristates charge pump output). Bringing EN

Main PLL.

9

10

CPo

MAIN

O

Main PLL Charge Pump output. Connected to a loop filter for driving the

control input of an external VCO.

10

11

V

CCMAIN

—

Main PLL power supply voltage input. Must be equal to V

range from 2.7V to 3.6V. Bypass capacitors should be placed as close

as possible to this pin and be connected directly to the ground plane.

11

12

fin

MAIN

I

Main prescaler input. Small signal input from the VCO.

12

13

GND

—

Main PLL ground.

13

14

LE

I

Load enable high impedance CMOS input. Data stored in the shift

registers is loaded into one of the 4 internal latches when LE goes HIGH

(control bit dependent).

14

15

Data

I

High impedance CMOS input. Binary serial data input. Data entered MSB

first. The last two bits are the control bits.

15

16

Clock

I

High impedance CMOS Clock input. Data for the various counters is

clocked in on the rising edge, into the 18-bit shift register.

www.national.com

3