PCB LAYOUT

BOOT

VSENSE

PH

VIN

GND

EN

Vout

PH

Vin

TOPSIDE

GROUND

AREA

OUTPUT

INDUCTOR

OUTPUT

FILTER

CAPACITOR

BOOT

CAPACITOR

INPUT

BYPASS

CAPACITOR

CATCH

DIODE

SignalVIA

RouteBOOT CAPACITOR

traceonotherlayertoprovide

widepathfortopsideground

RESISTOR

DIVIDER

Feedback Trace

COMP

SS

COMPENSATION

NETWORK

ThermalVIA

SLOWSTART

CAPACITOR

UVLO

RESISTOR

DIVIDER

ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS

TPS54331

The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to

minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch

diode. The typical recommended bypass capacitance is 10-

µF ceramic with a X5R or X7R dielectric and the

optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 14 for

a PCB layout example. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source

of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the

ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be

routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching

node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB

conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side

ground area must provide adequate heat dissipating area. The TPS54331 uses a fused lead frame so that the

GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of

internal or back side ground plane available, and the top side ground area can be connected to these areas

using multiple vias under or adjacent to the device to help dissipate heat. The additional external components

can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate

layout schemes, however this layout has been shown to produce good results and is intended as a guideline.

Figure 14. TPS54331 Board Layout

As EMI becomes a rising concern in more and more applications, the internal design of the TPS54331 takes

measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage

ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used

to lower the parasitics effects.

To achieve the best EMI performance, external component selection and board layout are equally important.

Follow the Step by Step Design Procedure above to prevent potential EMI issues.

Copyright © 2008, Texas Instruments Incorporated

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