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AD5024/AD5044/AD5064

Rev. 0 | Page 18 of 28

THEORY OF OPERATION

DAC SECTION

The AD5024/AD5044/AD5064 are single 12-/14-/16-bit, serial

input, voltage output DACs. The parts operate from supply voltages

of 4.5 V to 5.5 V. Data is written to the AD5024/AD5044/AD5064

in a 32-bit word format via a 3-wire serial interface. The AD5024/

AD5044/AD5064 incorporate a power-on reset circuit that ensures

that the DAC output powers up to a known output state. The

devices also have a software power-down mode that reduces the

typical current consumption to less than 2 μA.

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

⎟

⎠

⎞

⎜

⎝

⎛

REFIN

OUT

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 65,535 for the 16-bit AD5064).

N is the DAC resolution.

DAC ARCHITECTURE

The DAC architecture of the AD5064 consists of two matched

DAC sections. A simplified circuit diagram is shown in Figure 42.

The four MSBs of the 16-bit data word are decoded to drive 15

switches, E1 to E15. Each of these switches connects one of 15

matched resistors to either GND or the VREF buffer output. The

remaining 12 bits of the data-word drive the S0 to S11 switches

of a 12-bit voltage mode R-2R ladder network.

VREF

S11

E15

VOUT

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 42. DAC Ladder Structure

REFERENCE BUFFER

The AD5024/AD5044/AD5064 operate with an external reference.

Each DAC has a dedicated voltage reference pin. The reference

input pin has an input range of 2.5 V to VDD. This input voltage

is then used to provide a buffered reference for the DAC core.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages

on its output, which gives an output range of 0 V to VDD. The

amplifier is capable of driving a load of 5 kΩ in parallel with

200 pF to GND. The slew rate is 1.5 V/μs with a ¼ to ¾ scale

settling time of 13 μs.

SERIAL INTERFACE

The AD5024/AD5044/AD5064 have a 3-wire serial interface

(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI,

and MICROWIRE interface standards as well as most DSPs. See

for a timing diagram of a typical write sequence.

Figure 2

STANDALONE MODE

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5024/AD5044/AD5064 compatible

with high speed DSPs. On the 32nd falling clock edge, the last

data bit is clocked in and the programmed function is executed,

that is, a change in DAC register contents and/or a change in

the mode of operation. At this stage, the SYNC line can be kept

low or be brought high. In either case, it must be brought high

for a minimum of 1.9 μs (single channel) before the next write

sequence so that a falling edge of SYNC can initiate the next

write sequence. Because the SYNC buffer draws more current

when VIN = 2.2 V than it does when VIN = 0.8 V, SYNC should

be idled low between write sequences for even lower power

operation of the part. As mentioned previously, however, SYNC

must be brought high again just before the next write sequence.

Table 7. Command Definitions

Command

Description

Write to Input Register n

Update DAC Register n

Write to Input Register n, update all

(software LDAC)

Write to and update DAC Channel n

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Reserved

Table 8. Address Commands

Address (n)

Selected DAC

Channel

DAC A

DAC B

DAC C

DAC D

All DACs

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