AD5044 datasheet(20/28 Pages) AD

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AD5024/AD5044/AD5064

Rev. 0 | Page 20 of 28

POWER-ON RESET

The AD5024/AD5044/AD5064 contains a power-on reset

circuit that controls the output voltage during power-up. By

connecting the POR pin low, the AD5024/AD5044/AD5064

output powers up to zero scale. Note that this is outside the

linear region of the DAC; by connecting the POR pin high, the

AD5024/AD5044/AD5064 output powers up to midscale. The

output remains powered up at this level until a valid write

sequence is made to the DAC. This is useful in applications

where it is important to know the state of the output of the

DAC while it is in the process of powering up. There is also a

software executable reset function that resets the DAC to the

power-on reset code. Command 0111 is designated for this

reset function (see Table 7). Any events on LDAC or CLR

during power-on reset are ignored.

POWER-DOWN MODES

The AD5024/AD5044/AD5064 contain four separate modes of

operation. Command 0100 is designated for the power-down

function (see Table 7). These modes are software-programmable

by setting two bits, Bit DB9 and Bit DB8, in the control register

(Table 9). Table 9 shows how the state of the bits corresponds to

the mode of operation of the device. Any or all DACs (DAC D

to DAC A) can be powered down to the selected mode by

setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.

See Table 10 for the contents of the input shift register during

power-down/power-up operation.

When both Bit DB9 and Bit D8 in the control register are set to

0, the part works normally with its normal power consumption

of 3 mA at 5 V. However, for the three power-down modes, the

supply current falls to 0.4 μA at 5 V. Not only does the supply

current fall, but the output stage is also internally switched from

the output of the amplifier to a resistor network of known values.

This has the advantage that the output impedance of the part is

known while the part is in power-down mode. There are three

different options. The output is connected internally to GND

through either a 1 kΩ or a 100 kΩ resistor, or it is left open-

circuited (three-state). The output stage is illustrated in Figure 47.

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. However, the contents of the DAC register are

unaffected when in power-down. The time to exit power-down

is typically 4.5 μs for VDD = 5 V (see Figure 26).

Table 9. Modes of Operation

DB9

DB8

Operating Mode

Normal operation

Power-down modes:

1 kΩ to GND

100 kΩ to GND

Three-state

Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function

MSB

LSB

DB31

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB10

DB19

DB9

DB8

DB4

DB7

DB3

DB2

DB1

DB0

PD1

PD0

DAC D

DAC C

DAC B

DAC A

Don’t

cares

Command bits (C2 to C0)

Address bits (A3 to A0)—

don’t cares

Don’t

cares

Power-

down mode

Don’t

cares

Power-down/power-up channel

selection—set bit to 1 to select

RESISTOR

NETWORK

VOUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 47. Output Stage During Power-Down

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