AD5044 datasheet(23/28 Pages) AD

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AD5024/AD5044/AD5064

Rev. 0 | Page 23 of 28

MICROPROCESSOR INTERFACING

AD5024/AD5044/AD5064 to Blackfin ADSP-BF53x

Interface

Figure 48 shows a serial interface between the AD5024/AD5044/

AD5064 and the Blackfin® ADSP-BF53x microprocessor. The

ADSP-BF53x processor family incorporates two dual-channel

synchronous serial ports, SPORT1 and SPORT0, for serial and

multiprocessor communications. Using SPORT0 to connect to

the AD5024/AD5044/AD5064, the setup for the interface is as

follows: DT0PRI drives the DIN pin of the AD5024/AD5044/

AD5064, and TSCLK0 drives the SCLK of the parts. The SYNC

pin is driven from TFS0.

AD5024/

AD5044/

AD5064*

ADSP-BF53x*

SYNC

TFS0

DIN

DT0PRI

SCLK

TSCLK0

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 48. AD5024/AD5044/AD5064 to Blackfin ADSP-BF53x Interface

AD5024/AD5044/AD5064 to 68HC11/68L11 Interface

Figure 49 shows a serial interface between the AD5024/AD5044/

AD5064 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK of the AD5024/AD5044/AD5064,

and the MOSI output drives the serial data line of the DAC.

AD5024/

AD5044/

AD5064*

68HC11/68L11*

SYNC

PC7

SCLK

SCK

DIN

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 49. AD5024/AD5044/AD5064 to 68HC11/68L11 Interface

The SYNC signal is derived from a port line (PC7). The setup

conditions for correct operation of this interface are as follows:

The 68HC11/68L11 is configured with its CPOL bit as 0, and its

CPHA bit as 1. When data is being transmitted to the DAC, the

SYNC line is taken low (PC7). When the 68HC11/68L11 is

configured as described previously, data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11/68L11 is transmitted in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5024/AD5044/

AD5064, PC7 is left low after the first eight bits are transferred,

and a second serial write operation is performed to the DAC.

PC7 is taken high at the end of this procedure.

AD5024/AD5044/AD5064 to 80C51/80L51 Interface

Figure 50 shows a serial interface between the AD5024/AD5044/

AD5064 and the 80C51/80L51 microcontroller. The setup for

the interface is as follows: TxD of the 80C51/80L51 drives SCLK

of the AD5024/AD5044/AD5064, and RxD drives the serial

data line of the part. The SYNC signal is again derived from a

bit-programmable pin on the port. In this case, Port Line P3.3 is

used. When data is to be transmitted to the AD5024/AD5044/

AD5064, P3.3 is taken low. The 80C51/80L51 transmit data in

8-bit bytes only; thus, only eight falling clock edges occur in the

transmit cycle. To load data to the DAC, P3.3 is left low after the

first eight bits are transmitted, and a second write cycle is initiated

to transmit the second byte of data. P3.3 is taken high following

the completion of this cycle. The 80C51/80L51 output the serial

data in a format that has the LSB first. The AD5024/AD5044/

AD5064 must receive data with the MSB first. The 80C51/80L51

transmit routine should take this into account.

AD5024/

AD5044/

AD5064*

SYNC

P3.3

SCLK

TxD

DIN

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY.

80C51/80L51*

Figure 50. AD5024/AD5044/AD5064 to 80C512/80L51 Interface

AD5024/AD5044/AD5064 to MICROWIRE Interface

Figure 51 shows an interface between the AD5024/AD5044/

AD5064 and any MICROWIRE-compatible device. Serial data is

shifted out on the falling edge of the serial clock and is clocked into

the AD5024/AD5044/AD5064 on the rising edge of the SCLK.

AD5024/

AD5044/

AD5064*

SYNC

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

MICROWIRE*

Figure 51. AD5024/AD5044/AD5064 to MICROWIRE Interface

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