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DP80390 Datasheet(PDF) 60 Page - Digital Core Design

Part # DP80390
Description  Pipelined High Performance Microcontroller Instructions set details ver 3.10
PDF  84 Pages
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Manufacturer  DCD [Digital Core Design]
Direct Link  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design

DP80390 Datasheet(HTML) 60 Page - Digital Core Design

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DP80390 Instructions set details
- 60 -
All trademarks mentioned in this document
http://www.DigitalCoreDesign.com
are trademarks of their respective owners.
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
3.26.3.
MOVX @RI, A
Operation:
(PC)
← (PC) + 1
((Ri))
← (A)
Bytes:
1
Cycles:
4* – if MOVX CODE is executed from on-chip ROM or on-chip RAM,
and destination data are placed inside off-chip XRAM
5* – for all other cases as follow:
CODE inside off-chip XPRG, destination inside off-chip XRAM
CODE inside off-chip XPRG, destination inside off-chip XPRG
CODE inside off-chip XPRG, destination inside on-chip PRG RAM
CODE inside on-chip ROM, destination inside off-chip XPRG
CODE inside on-chip ROM, destination inside on-chip PRG RAM
CODE inside on-chip RAM, destination inside off-chip XPRG
CODE inside on-chip RAM, destination inside on-chip PRG RAM
Encoding:
1
1
1
1
0
0
1
i
3.26.4.
MOVX @DPTR, A
Operation:
(PC)
← (PC) + 1
((DPTR))
← (A)
Bytes:
1
Cycles:
3* – if MOVX CODE is executed from on-chip ROM or on-chip RAM,
and destination data are placed inside off-chip XRAM
4* – for all other cases as listed above
Encoding:
1
1
1
1
0
0
0
0
* MOVX cycles depends on READY pin. Shown values with 0 Wait-States.



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