IMX27 datasheet(75/122 Pages) FREESCALE

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Signal Descriptions

i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.6.9

SDRAM (DDR and SDR) Memory Controller

Figure 37, Figure 38, Figure 39, Figure 40, Figure 41, and Figure 42 depict the timings pertaining to the

ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 36, Table 37, Table 38, Table 39,

Table 40, and Table 41 list the timing parameters.

Figure 37. SDRAM Read Cycle Timing Diagram

Table 36. DDR/SDR SDRAM Read Cycle Timing Parameters

Parameter

Symbol

Min

Max

Unit

SD1

SDRAM clock high-level width

tCH

3.4

4.1

SD2

SDRAM clock low-level width

tCL

3.4

4.1

SD3

SDRAM clock cycle time

tCK

7.5

—

SD4

CS, RAS, CAS, WE, DQM, CKE setup time

tCMS

2.0

—

SD5

CS, RAS, CAS, WE, DQM, CKE hold time

tCMH

1.8

—

SDCLK

ADDR

DQM

COL/BA

Data

CAS

RAS

Note:

CKE is high during the read/write cycle.

SD4

SD1

SD3

SD2

SD4

SD5

SD6

SD7

SD10

SD8

SD9

SDCLK

ROW/BA

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