C164CI_02 datasheet(61/484 Pages) INFINEON

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C164CI/C164SI

Derivatives

Central Processing Unit (CPU)

User’s Manual

4-3

V3.1, 2002-02

A set of Special Function Registers is dedicated to the functions of the CPU core:

• General System Configuration

: SYSCON (RP0H)

• CPU Status Indication and Control

: PSW

• Code Access Control

: IP, CSP

• Data Paging Control

: DPP0, DPP1, DPP2, DPP3

• GPRs Access Control

: CP

• System Stack Access Control

: SP, STKUN, STKOV

• Multiply and Divide Support

: MDL, MDH, MDC

• ALU Constants Support

: ZEROS, ONES

4.1

Instruction Pipelining

The instruction pipeline of the C164CI partitions instruction processing into four stages,

each of which has a specific task:

1st

→ FETCH: In this stage, the instruction selected by the Instruction Pointer (IP) and

the Code Segment Pointer (CSP) is fetched from either the internal ROM, internal RAM,

or external memory.

2nd

→ DECODE: In this stage, the instructions are decoded and, if required, the operand

addresses are calculated and the respective operands are fetched. For all instructions

which implicitly access the system stack, the SP register is either decremented or

incremented as specified. For branch instructions, the Instruction Pointer and the Code

Segment Pointer are updated with the desired branch target address (provided that the

branch is taken).

3rd

→ EXECUTE: In this stage, an operation is performed on the previously fetched

operands in the ALU. Additionally, the condition flags in the PSW register are updated

as specified by the instruction. Also, all explicit writes to the SFR memory space and all

auto-increment or auto-decrement writes to GPRs used as indirect address pointers are

performed during the execute stage of an instruction.

4th

→ WRITE BACK: In this stage, all external operands and the remaining operands

within the internal RAM space are written back.

A special feature of the C164CI is the use of so-called injected instructions. Injected

instructions are generated internally by the machine to provide the time needed to

process instructions which cannot be processed within one machine cycle. These

instructions are injected automatically into the decode stage of the pipeline and then they

pass through the remaining stages like every standard instruction. Program interrupts

are performed by means of injected instructions, as well. Although these internally

injected instructions will not be noticed in reality, they are introduced here to ease the

explanation of the pipeline in the following sections.

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