C167CS-L datasheet(68/81 Pages) INFINEON

68 / 81 page

C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

Table 17

External Bus Cycle Timing (Operating Conditions apply)

Parameter

Symbol

Limits

Unit

min.

max.

Output delay from CLKOUT falling edge

Valid for: address (MUX on PORT0), write data out

tc10 CC 0

Output delay from CLKOUT edge

Valid for: latched CS, ALE (normal)

tc11 CC -3

Output delay from CLKOUT edge

Valid for: WR, WRL, WRH, WrCS

tc12 CC -4

Output delay from CLKOUT edge

Valid for: RD, RdCS

tc13 CC -2

Input setup time to CLKOUT falling edge

Valid for: read data in

tc14 SR 10

–

Input hold time after CLKOUT falling edge

Valid for: read data in1)

tc15 SR 0

–

Output delay from CLKOUT falling edge

Valid for: address (on PORT1 and/or P4), BHE

tc16 CC 0

92)

Output hold time after CLKOUT falling edge

Valid for: address, BHE3)

tc17 CC -2

Output hold time after CLKOUT edge4)

Valid for: write data out

tc18 CC -1

–

Output delay from CLKOUT falling edge

Valid for: ALE (extended), early CS

tc19 CC -4

Turn off delay after CLKOUT edge4)

Valid for: write data out

tc20 CC –

7ns

Turn on delay after CLKOUT falling edge4)

Valid for: write data out

tc21 CC -5

–

Output hold time after CLKOUT edge

Valid for: early CS

tc22 CC -6

1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles.

2) If the capacitive load on the respective output pins is limited to 30 pF the maximum output delay tc

16 can be

reduced to 8 ns.

3) Due to comparable propagation delays the address does not change before WR goes high. The minimum

output delay (

tc17min) is therefore the actual value of tc12.

4) Not 100% tested, guaranteed by design and characterization.

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