XC161 datasheet(49/419 Pages) INFINEON

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

User’s Manual

14-35

V2.2, 2004-01

GPT_X1, V2.0

Timer 6 Output Toggle Latch

The overflow/underflow signal of timer T6 is connected to a block named ‘Toggle Latch’,

shown in the timer mode diagrams. Figure 14-21 illustrates the details of this block. An

overflow or underflow of T6 will clock two latches: The first latch represents bit T6OTL in

control register T6CON. The second latch is an internal latch toggled by T6OTL’s output.

Both latch outputs are connected to the input control block of the auxiliary timer T5. The

output level of the shadow latch will match the output level of T6OTL, but is delayed by

one clock cycle. When the T6OTL value changes, this will result in a temporarily different

output level from T6OTL and the shadow latch, which can trigger the selected count

event in T5.

When software writes to T6OTL, both latches are set or cleared simultaneously. In this

case, both signals to the auxiliary timers carry the same level and no edge will be

detected. Bit T6OE (overflow/underflow output enable) in register T6CON enables the

state of T6OTL to be monitored via an external pin T6OUT. When T6OTL is linked to an

external port pin (must be configured as output), T6OUT can be used to control external

HW. If T6OE = 1, pin T6OUT outputs the state of T6OTL. If T6OE = 0, pin T6OUT

outputs a high level (while it selects the timer output signal).

As can be seen from Figure 14-21, when latch T6OTL is modified by software to

determine the state of the output line, also the internal shadow latch is set or cleared

accordingly. Therefore, no trigger condition is detected by T5 in this case.

Figure 14-21 Block Diagram of the Toggle Latch Logic of Core Timer T6

Note: T6 is also used to clock the timers in the CAPCOM units. For this purpose, there

is a direct internal connection between the T6 overflow/underflow line and the

CAPCOM timers (signal T6OUF).

m c_gpt0106_o tl.vsd

Togg le Latch Log ic

TxO U T

S e t/C le ar (S W )

Core T im e r

O verflow /

Un de rflo w

Shadow

Latch

Tx O E

TxO TL

To P ort Logic

To A ux. Tim e r

In pu t L o gic

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