XC161 datasheet(21/419 Pages) INFINEON

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XC161 Derivatives

Peripheral Units (Vol. 2 of 2)

The General Purpose Timer Units

User’s Manual

14-7

V2.2, 2004-01

GPT_X1, V2.0

Timer 3 Output Toggle Latch

The overflow/underflow signal of timer T3 is connected to a block named ‘Toggle Latch’,

shown in the timer mode diagrams. Figure 14-3 illustrates the details of this block. An

overflow or underflow of T3 will clock two latches: The first latch represents bit T3OTL in

control register T3CON. The second latch is an internal latch toggled by T3OTL’s output.

Both latch outputs are connected to the input control blocks of the auxiliary timers T2 and

T4. The output level of the shadow latch will match the output level of T3OTL, but is

delayed by one clock cycle. When the T3OTL value changes, this will result in a

temporarily different output level from T3OTL and the shadow latch, which can trigger

the selected count event in T2 and/or T4.

When software writes to T3OTL, both latches are set or cleared simultaneously. In this

case, both signals to the auxiliary timers carry the same level and no edge will be

detected. Bit T3OE (overflow/underflow output enable) in register T3CON enables the

state of T3OTL to be monitored via an external pin T3OUT. When T3OTL is linked to an

external port pin (must be configured as output), T3OUT can be used to control external

HW. If T3OE = 1, pin T3OUT outputs the state of T3OTL. If T3OE = 0, pin T3OUT

outputs a high level (as long as the T3OUT alternate function is selected for the port pin).

The trigger signals can serve as an input for the counter function or as a trigger source

for the reload function of the auxiliary timers T2 and T4.

As can be seen from Figure 14-3, when latch T3OTL is modified by software to

determine the state of the output line, also the internal shadow latch is set or cleared

accordingly. Therefore, no trigger condition is detected by T2/T4 in this case.

Figure 14-3

Block Diagram of the Toggle Latch Logic of Core Timer T3

m c_gpt0106_o tl.vsd

Togg le Latch Log ic

TxO U T

S e t/C le ar (S W )

Core T im e r

O verflow /

Un de rflo w

Shadow

Latch

Tx O E

TxO TL

To P ort Logic

To A ux. Tim e r

In pu t L o gic

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