DS5000 datasheet(5/19 Pages) DALLAS

5 / 19 page

DS5000(T)

021998 5/19

DS5000(T) LOGICAL ADDRESS SPACES Figure 2

64K

32K

NV RAM

PROGRAM

MEMORY

NV RAM

DATA

MEMORY

SPECIAL

FUNCTION

REGISTERS

DATA

REGISTERS

INTERNAL REGISTERS

LEGEND:

ON–CHIP REGISTERS

ACCESSED VIA EXPANDED BUS

NV RAM MEMORY

PROGRAM

MEMORY

DATA

MEMORY

PARTITION

ADDR.

RANGE

ADDR.

127

255

128

–

64K

32K

–

PROGRAM LOADING

The Program Load Modes allow initialization of the

NV RAM Program/Data Memory. This initialization may

be performed in one of two ways:

1. Serial Program Loading which is capable of per-

forming Bootstrap Loading of the DS5000(T). This

feature allows the loading of the application program

to be delayed until the DS5000(T) is installed in the

end system. Dallas Semiconductor strongly recom-

mends the use of serial program loading because of

its versatility and ease of use.

2. Parallel Program Load cycles which perform the ini-

tial loading from parallel address/data information

presented on the I/O port pins. This mode is timing–

set compatible with the 8751H microcontroller pro-

gramming mode.

The DS5000(T) is placed in its Program Load configura-

tion by simultaneously applying a logic 1 to the RST pin

and forcing the PSEN line to a logic 0 level. Immediately

following this action, the DS5000(T) will look for a paral-

lel Program Load pulse, or a serial ASCII carriage return

(0DH) character received at 9600, 2400, 1200, or 300

bps over the serial port.

The hardware configurations used to select these

modes of operation are illustrated in Figure 3.

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