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M48Z2M1Y Datasheet(PDF) 7 Page - STMicroelectronics |
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M48Z2M1Y Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 17 page ![]() 7/17 M48Z2M1Y, M48Z2M1V Table 3. READ Mode AC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 100pF or 50pF (see Figure 10., page 11). 3. CL = 5pF (see Figure 10., page 11). WRITE Mode The M48Z2M1Y/V is in the WRITE Mode whenev- er W and E are active. The start of a WRITE is ref- erenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tE- HAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms Note: Output Enable (G) = High. Symbol Parameter(1) M48Z2M1Y M48Z2M1V Unit –70 –85 Min Max Min Max tAVAV READ Cycle Time 70 85 ns tAVQV (2) Address Valid to Output Valid 70 85 ns tAXQX (2) Address Transition to Output Transition 5 5 ns tEHQZ (3) Chip Enable High to Output Hi-Z 30 35 ns tELQV (2) Chip Enable Low to Output Valid 70 85 ns tELQX (3) Chip Enable Low to Output Transition 5 5 ns tGHQZ (3) Output Enable High to Output Hi-Z 25 35 ns tGLQV (2) Output Enable Low to Output Valid 35 45 ns tGLQX (3) Output Enable Low to Output Transition 5 5 ns AI02053 tAVAV tWHAX tDVWH DATA INPUT A0-A20 E W DQ0-DQ7 VALID tAVWH tAVEL tWLWH tAVWL tWLQZ tWHDX tWHQX |
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