M48Z2M1Y datasheet(5/17 Pages) STMICROELECTRONICS

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M48Z2M1Y, M48Z2M1V

Figure 4. Block Diagram

OPERATION MODES

The M48Z2M1Y/V has its own Power-fail Detect

Circuit. The control circuitry constantly monitors

the single 5V supply for an out of tolerance condi-

tion. When VCC is out of tolerance, the circuit write

protects the SRAM, providing a high degree of

data security in the midst of unpredictable system

operations brought on by low VCC. As VCC falls be-

low approximately 3V, the control circuitry con-

nects the batteries which sustain data until valid

power returns.

Table 2. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

1. See Table 10., page 13 for details.

AI02050

INTERNAL

BATTERIES

VCC

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

2048K x 8

SRAM ARRAY

A0-A20

DQ0-DQ7

POWER

Mode

VCC

DQ0-DQ7

Power

Deselect

3.0 to 3.6V

4.5 to 5.5V

VIH

High Z

Standby

WRITE

VIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)

High Z

CMOS Standby

Deselect

≤ VSO(1)

High Z

Battery Back-up Mode

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