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LFSC Datasheet(PDF) 30 Page - Lattice Semiconductor |
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LFSC Datasheet(HTML) 30 Page - Lattice Semiconductor |
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30 / 237 page  2-26 Architecture Lattice Semiconductor LatticeSC/M Family Data Sheet 3. Bottom Side (Banks 4 and 5) These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential receivers are provided on all PIO pairs but true HLVDS, RSDS, and HYPT differential drivers are not available. Adaptive input logic is available on PIOs A or C. Table 2-8 lists the standards supported by each side. Table 2-8. I/O Standards Supported by Different Banks Supported Standards The LatticeSC PURESPEED I/O buffer supports both single-ended and differential standards. Single-ended stan- dards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVC- MOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP-2X33. Differential standards supported include LVDS, RSDS, BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O standards (together with their supply and reference voltages) supported by the LatticeSC devices. The tables also provide the available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer to support a variety of standards please see details of additional technical documentation at the end of this data sheet. Description Top Side Banks 1 Right Side Banks 2-3 Bottom Side Banks 4-5 Left Side Banks 6-7 I/O Buffer Type Single-ended, Differential Receiver Single-ended, Differen- tial Receiver and Driver Single-ended, Differential Receiver Single-ended, Differen- tial Receiver and Driver Output Standards Supported LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II SSTL33_ I, II HSTL15_I, II, III 1, IV1 HSTL18_I, II,III 1, IV1 SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II PCI33 PCIX15 PCIX33 AGP1X33 AGP2X33 MLVDS/BLVDS GTL 2, GTL+2 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II HSTL15_I,III HSTL18_I,II,III PCIX15 SSTL18D_I, II SSTL25D_I, II HSTL15D_I, II HSTL18D_I, II LVDS/RSDS/HYPT Mini-LVDS MLVDS/BLVDS GTL 2, GTL+2 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II SSTL33_ I, II HSTL15_I, II, III 1, IV1 HSTL18_I, II,III 1, IV1 SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II PCI33 PCIX15 PCIX33 AGP1X33 AGP2X33 MLVDS/BLVDS GTL 2, GTL+2 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II HSTL15_I,III HSTL18_I,II,III PCIX15 SSTL18D_I, II SSTL25D_I, II HSTL15D_I, II HSTL18D_I, II LVDS/RSDS/HYPT Mini-LVDS MLVDS/BLVDS GTL 2, GTL+2 Input Standards Supported Single-ended, Differential Single-ended, Differential Single-ended, Differential Single-ended, Differential Clock Inputs Single-ended, Differential Single-ended, Differential Single-ended, Differential Single-ended, Differential Differential Output Support via Emulation LVDS/MLVDS/BLVDS/ LVPECL MLVDS/BLVDS/ LVPECL LVDS/MLVDS/BLVDS/ LVPECL MLVDS/BLVDS/ LVPECL AIL Support No Yes Yes Yes 1. Input only. 2. Input only. Outputs supported by bussing multiple outputs together. |
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