EM78P142 datasheet(49/96 Pages) EMC

49 / 96 page

EM78P142

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 01.25.2008

• 43

(This specification is subject to change without further notice)

6.5.1.3

Controller Reset Block Diagram

WDT Timeout

Oscillator

CLK

CLR

WDT

VDD

Setup time

Reset

CLK

/RESET

Power-on Reset

Voltage

Detector

ENWDTB

Figure 6-7 Controller Reset Block Diagram

6.5.2 The T and P Status under Status Register

A reset condition is initiated by one of the following events:

1. Power-on reset

2. /RESET pin input "low"

3. WDT time-out (if enabled)

The values of T and P as listed in the table below, are used to check how the processor

wakes up.

Reset Type

RST

Power-on

/RESET during Operating mode,

/RESET wake-up during Sleep mode

LVR during Operating mode,

LVR wake-up during Sleep mode

WDT during Operating mode

WDT wake-up during Sleep mode

Wake-up on pin change during Sleep mode

P: Previous status before reset

The following shows the events that may affect the status of T and P.

Event

RST

Power-on

WDTC instruction

WDT time-out

SLEP instruction

Wake-up on pin changed during Sleep mode

*P: Previous value before reset

EM78P142 Datasheet(PDF) 49 Page - ELAN Microelectronics Corp

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