TAS3218IPZP datasheet(26/78 Pages) TI

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I2C Chip Select

GPIO Pins

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Power-Up Sequence

The rising edge of the RESET pin begins the initialization of housekeeping functions by clearing memory and

setting the default register values. After housekeeping initialization is complete, the TAS3218 enables the master

I2C interface. The TAS3218 then uses the master I2C interface to determine if an external memory device is

present.

External Memory Device Present

Using the master I2C interface, the TAS3218 will automatically test to see if an external memory device is at

address 1010xxx. The value xxx can be chip selects, other information, or dont care depending on the EEPROM

selected.

If an external memory device is present and it contains the correct header information along with one or more

blocks of program/memory data, the TAS3218 will automatically download the M8051 MCU program RAM,

coefficient and/or data RAM from the external EEPROM. This download is considered complete when an end of

program header is read by the TAS3218.

The memory block structure of the external memory device is available in Master I2C Load RAM Block Formats.

At this point, the TAS3218 will disable the master I2C interface, enable the slave I2C interface, and start normal

operation. After a successful download, the M8051 MCU program counter will be reset and the downloaded

M8051 MCU and DSP application firmware will control execution.

External Memory Device Not Present

If no external EEPROM is present or if an error occurred during the external memory device read, the TAS3218

will disable the master I2C interface, enable the slave I2C interface. The default slave configuration will then be

loaded from the ROM into the M8051 MCU and DSP. In this default configuration, the TAS3218 will stream audio

from input to output if the GPIO1 pin pulled LOW.

NOTE:

The master and slave interfaces do not operate simultaneously, thus when one

interface is enabled, the other is disabled.

The CS pin on the TAS3218 allows up to two TAS3218 devices to be addressed by the I2C bus via an external

host controller without the need for external logic. Table 5 and Table 6 list the I2C address for each I2C interface.

Table 5.

I2C Slave Addressing

SLAVE ADDRESS

0x68/69

0x6A/6B

Table 6.

I2C Master Addressing

SLAVE ADDRESS

0xA0/A1

0xA2/A3

The TAS3218 has two level-sensitive GPIO pins, GPIO1 and GPIO2, that are firmware programmable. Upon

power up or following a RESET, the GPIO1 pin becomes an input, and has a special function as described in

GPIO1 Pin Function.

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TAS3218IPZP Datasheet(PDF) 26 Page - Texas Instruments

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