TUSB6015ZQE

SLLS937

REVISION 1.4 SEPTEMBER 10, 2008

Synchronous Burst Read Access

Notes: RDY going low is asynchronous to t_scsn_rdy. Going high, it is synchronous to CLK. Read Data output and RDY going high are

synchronous to CLK. Valid Data Time programmable through Device Wait Count Register. Wait Count is not used for non-DMA

synchronous reads.

PARAMETER

MIN

MAX

UNIT

t_clk

Cycle Time (max 67.5 MHz)

14.8

ns

t_scsnh_scsnl

Delay time, SCSn high to SCSn low

8

ns

t_acsnh_scsnl

Delay time, ACSn high to SCSn low

8

ns

t_scsn

Delay time, SCSn low to first rising edge of CLK

3ns

1+3ns

CLK

t_scs_off

CLK to SCSn high

4

ns

t_rdata

Read data output delay

2.2

9.2

ns

t_rdy

RDY output delay

2.2

8.2

Ns

t_advn

ADVn low pulse

7

Ns

t_advn_oen

ADVn high to OEn low

3

Ns

t_oen_off

CLK to OEn high

4

Ns

OEn setup to CLK high

3.75

Ns

t_oen

OEn hold time

0

t_rd_acc

Valid Data Time (with DMAREQ)

1

1

32

2

CLK

t_add_advn_h

Addr Hold time to ADVn high

0.8

Ns

t_scsnl_advn_s

SCSn low Setup to ADVn high

12

Ns

t_add_advn_s

Address Setup to ADVn high

12

Ns

t_scsn_rdy

SCSn low to RDY valid low

7

ns

t_scsn_rdy_z

SCSn high to RDY high-Z

7

ns

t_oen_data_z

OEn high to Data high-Z

8

ns

1

Device Wait Count Register = 0 or 1.

2

Device Wait Count Register = 31.

15

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