34844 datasheet(18/37 Pages) FREESCALE

18 / 37 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

34844

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

NORMAL MODE

In normal operation the 34844 is programed via I2C to

drive up to 50mA of current through each one of the LED

channels. The 34844 can be configured in master or slave

mode as set by the M/~S pin.

In Master mode, the internal PWM generator frequency is

programmed through the I2C interface. The programmed

value sets the number of 25kHz clocks (40

μs) in one PWM

cycle. The 18-bit resolution allows minimum PWM

frequencies of 100Hz to be programmed. The resulting

frequency is output on the CK pin.

In slave mode, the CK pin acts as an input. The internal

digital PLL uses this frequency as the PWM frequency.

By setting one device as a master, and connecting the CK

output to the input on a number of slave configured devices,

all PWM frequencies are synchronized together. For this

application A0/SEN pin indicates which device is enable for

I2C control.

In Slave mode, an internal phase lock loop will lock the

internal PWM generator period to the period of the signal

present at the CK pin. The PLL can lock to any frequency

from 100Hz to 25KHz provided the jitter is below 1000ppm.

At frequencies above 1KHz, the PLL will maintain lock

regardless of the transient power conditions imposed by the

user (i.e. going from 0% duty cycle to 100% at 20W LED

display power). Below 1kHz, thermal time constants on the

die are such that the PLL may momentarily lose lock if the die

temperature changes substantially during a large load power

step. As explained below, this anomaly can be avoided by

controlling the rate of change in PWM duty cycle.

To better understand this issue, consider that the on chip

PLL uses a VCO that is subject to thermal drift on the order

of 1000 ppm/C. Further consider that the thermal time

constant of the chip is on the order of single digit

milliseconds. Therefore, if a large power load step is imposed

by the user (i.e. going from 0% duty cycle to 100% duty cycle

with a load power of 20W), the die will experience a large

temperature wave gradient that will propagate across the

chip surface and thereby affect the instantaneous frequency

of the VCO. As long as such changes are within the

bandwidth of the PLL, the PLL will be able to track and

maintain lock. Exceeding this rate of change may cause the

PLL to lose lock and the backlight will momentarily be

blanked until lock is reacquired.

At 100Hz lock, the PLL has a bandwidth of approximately

10Hz. This means that temperature changes on the order of

100ms are tolerable without losing lock. But full load power

changes on the order of 10ms (i.e. 100Hz PWM) are not

tracked out and the PLL can momentarily lose lock. If this

happens, as stated above, the LED drivers are momentarily

disabled until lock is reacquired. This will be manifested as a

perceivable short flash on the backlight immediately after the

load change.

To avoid this problem, one can simply limit large

instantaneous changes in die temperature by invoking only

small power steps when raising or lowering the display power

at low PWM frequencies. For example, to maintain lock while

transitioning from 0% to 100% duty cycle at 20W load power

and a PWM frequency of 100Hz would entail stepping the

power at a rate not to exceed 1% per 10ms. If a load of less

than 20W is used, then the rate of rise can be increased. As

the locked PWM frequency increases (i.e. use 600Hz instead

of 100Hz), the step rate can be further increased to

approximately 4% per 2ms. The exact step rate to avoid loss

of PLL lock is a function of essentially three things: (a) the

composite thermal resistance of the user's PCB assembly, (b)

the load power, and (c) the PWM frequency. For all cases

below 1KHz, simply using a rate of 1% duty cycle change per

PWM period will be adequate. If this is too slow, the value can

be optimized experimentally once the hardware design is

complete. At PWM rates above 1KHz, it is not necessary to

control the rate of change in PWM duty cycle.

It is important to point out that when operating in the

master mode, one does not need to concern themselves with

loss of lock since the reference clock and the VCO clock are

collocated on the die and therefore experience the same

thermal shift. Hence, in master mode, once lock is initially

acquired, it is not lost and no blanking of the display occurs.

The duty cycle of the PWM in both master and slave mode

is set using a second register on the I2C interface.

An external PWM signal can also be applied in the PWM

pin. This pin is AND’ed with the internal signal, giving the

ability to control the duty cycle either via I2C or externally by

setting any of the 2 signals to 100% duty cycle.

STROBE MODE

A strobe mode can be programmed via I2C.

In this mode, each rising edge of the PWM signal turns on

the next channel, while turning off all other channels. The

duration that the channel is illuminated is set by the duty cycle

of the PWM input pin.

This mode can be also programmed by controlling the ON

and OFF state of each LED channel via I2C.

MANUAL MODE

The 34844 can also be used in Manual mode without using

the I2C interface. By setting the pin M/~S High, the LED

dimming will be controlled by the external PWM signal. The

over-voltage protection limit can be settled by a resistor

divider on A0/SEN pin.

During manual mode, all internal Registers are in Default

Configuration, please refer Table 7, under this configuration

34844 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

34844 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL