16C6KA datasheet(13/268 Pages) RENESAS

13 / 268 page

M16C/6KA Group

CPU

Rev.1.00

Jul 16, 2004

page 13 of 266

REJ03B0100-0100Z

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Fig.BA-1 Seven of these registers (R0, R1, R2, R3, A0, A1, and

FB) come in two sets; therefore, these have two register banks.

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and

arithmetic/logic operations.

Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and

low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-

bit data registers (R2R0/R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data

registers. These registers can also be u2sed for address register indirect addressing and address register

relative addressing.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Fig.BA-1 Central processing unit register

b15

b8 b7

R0(Note)

b15

b8 b7

R1(Note)

R2(Note)

b15

R3(Note)

b15

A0(Note)

b15

A1(Note)

b15

FB(Note)

b15

Data

registers

Address

registers

Frame base

b15

b19

Program counter

Interrupt table

User stack pointer

Interrupt stack

pointer

Static base

Flag register

INTB

USP

ISP

FLG

Note: These registers consist of two register banks.

IPL

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