38K2 datasheet(116/151 Pages) RENESAS

116 / 151 page

38K2 Group

Rev.3.00

Oct 15, 2006

page 116 of 147

REJ03B0193-0300

Fig. 157 Timing for clear status register

qClear Status Register Command

This command clears the bits (SR3 to SR5) which are set when

the status register operation ends in error. When the “5016” com-

mand code is sent with the 1st byte, the aforementioned bits are

cleared. When the clear status register operation ends, the SRDY

(BUSY) signal changes from “H” to “L” level.

SCLK

RxD

TxD

SRDY (BUSY)

5016

A8 to

A15

A16 to

A23

4116

data0

data255

SCLK

RxD

TxD

SRDY (BUSY)

qPage Program Command

This command writes the specified page (256 bytes) in the flash

memory sequentially one byte at a time. Execute the page pro-

gram command as explained here following.

(1) Transfer the “4116” command code with the 1st byte.

(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and

3rd bytes respectively.

(3) From the 4th byte onward, as write data (D0 to D7) for the

page (256 bytes) specified with addresses A8 to A23 is input

sequentially from the smallest address first, that page is auto-

matically written.

When reception setup for the next 256 bytes ends, the SRDY

(BUSY) signal changes from “H” to “L” level. The result of the

page program can be known by reading the status register. For

more information, see the section on the status register.

Fig. 158 Timing for page program

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