38K2 datasheet(19/151 Pages) RENESAS

19 / 151 page

38K2 Group

Rev.3.00

Oct 15, 2006

page 19 of 147

REJ03B0193-0300

TIMERS

The 38K2 group has three timers: timer X, timer 1, and timer 2.

The division ratio of each timer or prescaler is given by 1/(n + 1),

where n is the value in the corresponding timer or prescaler latch.

All timers are down count timers. When the timer reaches “0016”,

an underflow occurs at the next count pulse and the correspond-

ing timer latch is reloaded into the timer and the count is contin-

ued. When a timer underflows, the interrupt request bit corre-

sponding to that timer is set to “1”.

Fig. 16 Structure of timer X mode register

Timer 1 and Timer 2

The count source of prescaler 12 is the system clock divided by

16. The output of prescaler 12 is counted by timer 1 and timer 2,

and a timer underflow periodically sets the interrupt request bit.

Timer X

Timer X can each select in one of four operating modes by setting

the timer X mode register.

(1) Timer Mode

The timer counts the count source selected by timer count source

selection bit.

(2) Pulse Output Mode

The timer counts the system clock divided by 16. Whenever the

contents of the timer reach “0016”, the signal output from the

CNTR0 pin is inverted. If the CNTR0 active edge selection bit is

“0”, output begins at “ H”.

If it is “1”, output starts at “L”. When using a timer in this mode, set

the corresponding port P51 direction register to output mode.

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode,

except that the timer counts signals input through the CNTR0 pin.

When the CNTR0 active edge selection bit is “0”, the rising edge of

the CNTR0 pin is counted.

When the CNTR0 active edge selection bit is “1”, the falling edge

of the CNTR0 pin is counted.

(4) Pulse Width Measurement Mode

If the CNTR0 active edge selection bit is “0”, the timer counts the

system clock divided by 16 while the CNTR0 pin is at “H”. If the

CNTR0 active edge selection bit is “1”, the timer counts it while the

CNTR0 pin is at “L”.

The count can be stopped by setting “1” to the timer X count stop

bit in any mode. The corresponding interrupt request bit is set

each time a timer underflows.

Timer X mode register

(TM : address 002316)

Timer X operating mode bits

b1 b0

00 : Timer mode

01 : Pulse output mode

10 : Event counter mode

11 : Pulse width measurement mode

CNTR0 active edge switch bit

0 : Falling edge active for CNTR0 interrupt

Count at rising edge in event counter mode

1 : Rising edge active for CNTR0 interrupt

Count at falling edge in event counter mode

Timer X count stop bit

0 : Count start

1 : Count stop

Not used (return “0” when read)

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