R8CSLASH15 datasheet(11/40 Pages) RENESAS

11 / 40 page

Rev.2.00

Jan 30, 2006

Page 11 of 37

REJ03B0102-0200

R8C/14 Group, R8C/15 Group

2. Central Processing Unit (CPU)

2.1

Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The

R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data

registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used

as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.

2.2

Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing.

They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can

be combined with A0 to be used as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register indicates the start address of an interrupt vector table.

2.5

Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch

between USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8

Flag Register (FLG)

FLG is a 11-bit register indicating the CPU state.

2.8.1

Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.

2.8.2

Debug Flag (D)

The D flag is for debug only. Set to “0”.

2.8.3

Zero Flag (Z)

The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.

2.8.4

Sign Flag (S)

The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.

2.8.5

The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is set

to “1”.

2.8.6

Overflow Flag (O)

The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.

R8C/15 Datasheet(PDF) 11 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 11 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL