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R8C/15 Datasheet(PDF) 25 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 25 Page - Renesas Technology Corp |
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25 / 40 page ![]() Rev.2.00 Jan 30, 2006 Page 25 of 37 REJ03B0102-0200 R8C/14 Group, R8C/15 Group 5. Electrical Characteristics NOTES: 1. The measurement condition is VCC = AVCC = 5.0V and Topr = 25 °C. 2. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to 00h. NOTES: 1. The measurement condition is VCC = AVCC = 2.7 to 5.5V and Topr = 25 °C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode. NOTES: 1. VCC = AVCC = 2.7 to 5.5V, VSS = 0V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified. 2. 1tCYC = 1/f1(s) Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard Unit Min. Typ. Max. − High-Speed On-Chip Oscillator Frequency When the Reset is Deasserted VCC = 5.0V, Topr = 25 °C − 8 − MHz − High-Speed On-Chip Oscillator Frequency Temperature • Supplay Voltage Dependence 0 to +60 °C / 5 V ± 5 %(2) 7.44 − 8.56 MHz −20 to +85 °C / 2.7 to 5.5 V(2) 7.04 − 8.96 MHz −40 to +85 °C / 2.7 to 5.5 V(2) 6.80 − 9.20 MHz Table 5.11 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard Unit Min. Typ. Max. td(P-R) Time for Internal Power Supply Stabilization during Power-On(2) 1 − 2000 µs td(R-S) STOP Exit Time(3) −− 150 µs Table 5.12 Timing Requirements of Clock Synchronous Serial I/O (SSU) with Chip Select(1) Symbol Parameter Conditions Standard Unit Min. Typ. Max. tSUCYC SSCK Clock Cycle Time 4 −− tCYC(2) tHI SSCK Clock “H” Width 0.4 − 0.6 tSUCYC tLO SSCK Clock “L” Width 0.4 − 0.6 tSUCYC tRISE SSCK Clock Rising Time Master −− 1 tCYC(2) Slave −− 1 µs tFALL SSCK Clock Falling Time Master −− 1 tCYC(2) Slave −− 1 µs tSU SSO, SSI Data Input Setup Time 100 −− ns tH SSO, SSI Data Input Hold Time 1 −− tCYC(2) tLEAD SCS Setup Time Slave 1tCYC+50 −− ns tLAG SCS Hold Time Slave 1tCYC+50 −− ns tOD SSO, SSI Data Output Delay Time −− 1 tCYC(2) tSA SSI Slave Access Time −− 1.5tCYC+100 ns tOR SSI Slave Out Open Time −− 1.5tCYC+100 ns |
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