R8CSLASH15 datasheet(12/40 Pages) RENESAS

12 / 40 page

Rev.2.00

Jan 30, 2006

Page 12 of 37

REJ03B0102-0200

R8C/14 Group, R8C/15 Group

2. Central Processing Unit (CPU)

2.8.7

Interrupt Enable Flag (I Flag)

The I flag enables a maskable interrupt.

An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The I

flag is set to “0” when an interrupt request is acknowledged.

2.8.8

Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.

The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of

software interrupt numbers 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10

Reserved Bit

When write to this bit, set to “0”. When read, its content is indeterminate.

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