HD404372 datasheet(49/161 Pages) RENESAS

49 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 49 of 161

Watch mode is cleared by

RESET input or an INT

0,timer A or WU0 interrupt request.

For

RESET input,

refer to the section on stop mode. When watch mode is cleared by an

INT

0, timer A or WU0 interrupt

request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if LSON =

0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt request

generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the timer A

interrupt, and, for the INT

0 interrupt or WU0 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1 and 0 (MIS1,

MIS0) of the miscellaneous register are set to 00, or Tx (t

RC < Tx < T + tRC) if MIS1 and MIS0 are set to 01

or 10 (figures 14 and 15). Other operations when the transition is made are the same as when watch mode

is cleared (figure 12).

Subactive mode ( Applies to HD404374 Series):

In subactive mode, the OSC

1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated

by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but

since the operating clocks are slow, power consumption is the lowest after watch mode.

A CPU instruction processing speed of 244 µs or 122 µs can be selected according to whether bit 2 (SSR2)

of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should

be changed (0

→1 or 1→0) only in active mode. If the value is changed in subactive mode, the MCU may

operate incorrectly.

Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch

mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct transfer

on flag (DTON: $020,3).

Subactive mode is a function option, and should be specified in the function option list.

Interrupt frame ( Applies to HD404374 Series):

In watch mode and subactive mode, ø

CLK is supplied to the timer A, WU0, and INT0 acceptance circuits.

Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two values

can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005)

(figure 15).

In watch mode and subactive mode, the timing for generation of timer A,

INT

0 and WU0 interrupts is

synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt strobe

timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at the

interrupt strobe timing.

HD404372 Datasheet(PDF) 49 Page - Renesas Technology Corp

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