HD404372 datasheet(62/161 Pages) RENESAS

62 / 161 page

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Rev.5.00, Sep.11.2003, page 62 of 161

D Port

The D port consists of 10 I/O pins that are addressed bit-by-bit.

Ports D

0 to D3 are source large-current I/O pins, and ports D4 to D7 are sink large-current I/O pins.

The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD

or TDD instruction.

The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to

$032). The DCD registers are mapped onto memory addresses (figure 25).

Port D

0 is multiplexed as interrupt input pin INT0.

Setting as interrupt pin is performed by bit 0 (PMR00)

of port mode register 0 (PMR0: $008) (figure 26).

Data control registers (DCD0–2 : $030–$032)

(DCR0–2, 7 : $034–$036, $03B)

DCDn

DCRm

Bit

Read/Write

Reset

Bit name

Read/Write

Reset

Bit name

DCDn3

DCRm3

DCDn2

DCRm2

DCDn1

DCRm1

DCDn0

DCRm0

All bits

CMOS buffer off (high impedance)

CMOS buffer active

CMOS buffer control

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR7

Bit 3

R13

R73

Bit 2

R22

R72

Bit 1

R21

R71

Bit 0

R00

R10

R20

R70

Correspondence between each bit of DCD and DCR and ports

(n=0 to 2)

(m=0 to 2, 7)

Figure 25 Data Control Registers (DCD, DCR)

HD404372 Datasheet(PDF) 62 Page - Renesas Technology Corp

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