4519 datasheet(59/162 Pages) RENESAS

59 / 162 page

4519 Group

Rev.3.01

2005.06.15

page 59 of 160

REJ03B0007-0301

Fig. 48 Structure of reset pin and its peripherals,, and power-on reset operation

Name

D0–D5

D6/CNTR0

D7/CNTR1

P00–P03

P10–P13

P20/SCK, P21/SOUT, P22/SIN

P30/INT0, P31/INT1, P32, P33

P40/AIN4–P43/AIN7

P50–P53

P60/AIN0–P63/AIN3

Notes 1: Output latch is set to “1.”

2: Output structure is N-channel open-drain.

3: Pull-up transistor is turned OFF.

Function

D0–D5

P00–P03

P10–P13

P20–P22

P30–P33

P40–P43

P50–P53

P60–P63

State

High-impedance (Notes 1, 2)

High-impedance (Notes 1, 2, 3)

High-impedance (Note 1)

High-impedance (Notes 1, 2)

High-impedance (Note 1)

(1) Power-on reset

Reset can be automatically performed at power on (power-on re-

set) by the built-in power-on reset circuit. When the built-in

power-on reset circuit is used, the time for the supply voltage to

rise from 0 V until the value of supply voltage reaches the minimum

operating voltage must be set to 100

µs or less.

If the rising time exceeds 100

µs, connect a capacitor between the

RESET pin and VSS at the shortest distance, and input “L” level to

RESET pin until the value of supply voltage reaches the minimum

operating voltage.

Table 1 Port state at reset

RESET pin

WEF

Watchdog reset signal

(Note 1)

Pull-up transistor

(Note 1)

Power-on reset circuit

Voltage drop detection circuit

VDD (Note 3)

100

µs or less

(Note 2)

Internal reset signal

Power-on

Reset released

Internal reset signal

Reset

state

Notes 1:

This symbol represents a parasitic diode.

2: Applied potential to RESET pin must be VDD or less.

3: Keep the value of supply voltage to the minimum value

or more of the recommended operating conditions.

Power-on reset circuit output

SRST instruction

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