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4551 Datasheet(PDF) 59 Page - Renesas Technology Corp |
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4551 Datasheet(HTML) 59 Page - Renesas Technology Corp |
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59 / 69 page ![]() 58 MITSUBISHI MICROCOMPUTERS 4551 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER CONTROL REGISTERS V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt control register V1 at reset : 00002 at power down : 00002 R/W Prescaler control bit Prescaler dividing ratio selection bit Timer 1 count source selection bits Timer control register W1 W13 W12 W11 W10 at reset : 00002 at power down : 00002 0 1 0 1 R/W Stop (prescaler state initialized) Operating Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 8 Count source Prescaler output (ORCLK) Carrier output (CARRY) Carrier output divided by 2 (CARRY/2) W11 0 0 1 1 W10 0 1 0 1 Timer control register W2 at reset : 10002 at power down : – – – 02 R/W 0 1 f(XCIN) Prescaler output (ORCLK) W23 W22 W21 W20 Timer 2 count source selection bit Timer 2 count value selection bits Timer 1 control bit W22 0 0 1 1 W21 0 1 0 1 Count source Underflow occur every 214 count Underflow occur every 213 count Not available Not available Stop (timer 1 state retained) Operating 0 1 Timer control register W3 at reset : 002 at power down : state retained R/W 0 1 0 1 Bit 3 of timer 2 is output (timer 2 count source divided by 16) State clock (STCK) Stop (timer LC state retained) Operating W31 W30 Timer LC count source selection bit Timer LC control bit Note: “R” represents read enabled, and “W” represents write enabled. “–” represents state retained. |
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