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M37702S1AFP Datasheet(PDF) 13 Page - Renesas Technology Corp |
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M37702S1AFP Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 60 page  12 MITSUBISHI MICROCOMPUTERS M37702M2AXXXFP, M37702M2BXXXFP M37702S1AFP, M37702S1BFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER INTERRUPTS Table 1 shows the interrupt types and the corresponding interrupt vector addresses. Reset is also treated as a type of interrupt and ____ is discussed in this section, too. DBC is an interrupt used during debugging. ____ Interrupts other than reset, DBC, watchdog timer, zero divide, and BRK instruction all have interrupt control registers. Table 2 shows the addresses of the interrupt control registers and Figure 6 shows the bit configuration of the interrupt control register. Use the SEB and CLB instructions when setting each interrupt control register. The interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. ____ Also, interrupt request bits other than DBC and watchdog timer can be cleared by software. ____ ____ INT2 to INT0 are external interrupts and whether to cause an inter- rupt at the input level (level sense) or at the edge (edge sense) can be selected with the level sense/edge sense selection bit. Fur- thermore, the polarity of the interrupt input can be selected with polarity selection bit. Timer and UART interrupts are described in the respective sec- tion. The priority of interrupts when multiple interrupts are caused simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in Figure 7. The hardware priority is fixed the following: ____ reset > DBC > watchdog timer > other interrupts Interrupts A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 ____ INT2 external interrupt ____ INT1 external interrupt ____ INT0 external interrupt Watchdog timer ____ DBC (unusable) Break instruction Zero divide Reset Vector addresses 00FFD616 00FFD716 00FFD816 00FFD916 00FFDA16 00FFDB16 00FFDC16 00FFDD16 00FFDE16 00FFDF16 00FFE016 00FFE116 00FFE216 00FFE316 00FFE416 00FFE516 00FFE616 00FFE716 00FFE816 00FFE916 00FFEA16 00FFEB16 00FFEC16 00FFED16 00FFEE16 00FFEF16 00FFF016 00FFF116 00FFF216 00FFF316 00FFF416 00FFF516 00FFF616 00FFF716 00FFF816 00FFF916 00FFFA16 00FFFB16 00FFFC16 00FFFD16 00FFFE16 00FFFF16 Table 1. Interrupt types and the interrupt vector addresses Fig. 6 Interrupt control register configuration 7 Interrupt priority 654 3 2 1 0 Interrupt request bit 0 : No interrupt 1 : Interrupt Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2 7 Interrupt priority 654 3 2 1 0 Interrupt request bit 0 : No interrupt 1 : Interrupt Polarity selection bit 0 : Set interrupt request bit at “H” level for level sense and when changing from “H” to “L” level for edge sense. 1 : Set interrupt request bit at “L” level for level sense and when changing from “L” to “H” level for edge sense. Level sense/edge sense selection bit 0 : Edge sense 1 : Level sense Interrupt control register configuration for INT2 to INT0. |
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