HA16116FP/FPJ, HA16121FP/FPJ

Rev.2.0, Sep.18.2003, page 13 of 33

4. Totem Pole Output Stage Circuit and Power MOS FET Driving Method

The output stage of this IC series is configured of totem pole circuits, allowing direct connection to a power

MOS FET as an external switching device, so long as V

If there is a possibility that V

diode circuit like that shown figure 4.1 or other protective measures should be used. The figure 4.1 shows

an example using a P-channel power MOS FET.

Bias

circuit

OUT

Zener diode for

gate protection

Drive circuit

Gate

protection

resistor

Schottky

barrier diode

+

−

Figure 4.1 P-channel Power MOS FET (example)

5. Vref Undervoltage Error Prevention (UVL) and Overvoltage Protection (OVP) Functions

5.1 Operation Principles

The reference voltage circuit is equipped with UVL and OVP functions.

• UVL

In normal operation the Vref output voltage is fixed at 2.5 V. If V

circuit detects the Vref output voltage with a hysteresis of 1.7 V and 2.0 V, and shuts off the PWM

output if Vref falls below this level, in order to prevent malfunction.

• OVP

The OVP circuit protects the IC from inadvertent application of a high voltage from outside, such as if

V

A Zener diode (5.6 V) and resistor are used between Vref and GND for overvoltage

detection. PWM output is shut off if Vref exceeds approximately 7.0 V.

Note that the PWM output pulse logic and the precision of the switching regulator output voltage are not

guaranteed at an applied voltage of 2.5 V to 7 V.