SH7145 datasheet(49/930 Pages) RENESAS

49 / 930 page

1. Overview

Rev.4.00 Mar. 27, 2008 Page 5 of 882

REJ09B0108-0400

RES

WDTOVF

MD3

MD2

MD1

MD0

NMI

EXTAL

XTAL

PLLVcc

PLLCAP

PLLVss

FWP*

Vcc

Vss

AVcc

AVref

AVss

DBGMD

ASEBRKAK

CPU

RAM

8kB

PD31/D31/

ADTRG

PD30/D30/

IRQOUT

PD29/D29/

CS3

PD28/D28/

CS2

PD27/D27/DACK1

PD26/D26/DACK0

PD25/D25/

DREQ1

PD24/D24/

DREQ0

PD23/D23/

IRQ7/AUDSYNC

PD22/D22/

IRQ6/AUDCK

PD21/D21/

IRQ5/AUDMD

PD20/D20/

IRQ4/AUDRST

PD19/D19/

IRQ3/AUDATA3

PD18/D18/

IRQ2/AUDATA2

PD17/D17/

IRQ1/AUDATA1

PD16/D16/

IRQ0/AUDATA0

H-UDI*

PD15/D15

PD14/D14

PD13/D13

PD12/D12

PD11/D11

PD10/D10

PD9/D9

PD8/D8

PD7/D7

PD6/D6

PD5/D5

PD4/D4

PD3/D3

PD2/D2

PD1/D1

PD0/D0

PC15/A15

PC14/A14

PC13/A13

PC12/A12

PC11/A11

PC10/A10

PC9/A9

PC8/A8

PC7/A7

PC6/A6

PC5/A5

PC4/A4

PC3/A3

PC2/A2

PC1/A1

PC0/A0

AUD*

Note: * Pin and modules for the F-ZTAT reision only

Serial communication

interface

(

× 4 channels)

Compare match

timer

(

× 2 channels)

2C bus interface

Interrupt

controller

User break

controller

Bus state

controller

A/D

converter

Watchdog

timer

Multifunction

timer pulse unit

Data transfer

Controller

Direct memory

access controller

Flash ROM/

mask ROM

256kB

Peripheral address bus (12bits)

Peripheral data bus (16bits)

Internal address bus (32bits)

Internal upper data bus (16bits)

Internal lower data bus (16bits)

Figure 1.2 Block Diagram of SH7145

SH7145 Datasheet(PDF) 49 Page - Renesas Technology Corp

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