M32C83T datasheet(352/527 Pages) RENESAS

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Page 329

22. CAN Module

)

(

22.1.2 CAN0 Control Register 1 (C0CTLR1 Register)

BANKSEL

(b1 - b0)

(b2)

(b5 - b4)

(b7 - b6)

CAN0 Control Register 1

Symbol

Address

After Reset(1)

C0CTLR1

024116

XX00 00XX2

CAN0 Bank Switch Bit

0 : Selects the message slot control

1 : Selects the masked register

Bit Name

Function

Bit

Symbol

Reserved Bit

Set to "0"

Reserved Bit

Set to "0"

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

NOTES:

1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and

supplying a clock to the CAN module after reset.

Figure 22.4 C0CTLR1 Register

22.1.2.1 BANKSEL Bit

The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 022016 to

023F16.

The C0MCTL0 to C0MCTL15 registers can be accessed by setting the BANKSEL bit to "0". The

C0GMR0 to C0GMR4 registers, C0LMAR0 to C0LMAR4 registers and C0LMBR0 to C0LMBR4 reg-

isters can be accessed by setting the BANKSEL bit to "1".

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