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M32C83T Datasheet(PDF) 253 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 253 Page - Renesas Technology Corp |
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253 / 527 page ![]() Page 230 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 17. A/D Converter ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Function A/D0 Control Register 2(1) Bit Name Bit Symbol Symbol Address After Reset AD0CON2 039416 X000 00002 RW RW RW RW RW RW WO SMP ADS (b3 - b1) TRG0 TRG1 A/D Conversion Method Select Bit 0 : Without the sample and hold function 1 : With the sample and hold function Reserved Bit Set to "0" 0 : Disables channel replacement 1 : Enables channel replacement(5) PST External Trigger Request Cause Select Bit A/D Channel Replace Select Bit(2) Simultaneous Start Bit(2, 3, 4) b6 b5 When this bit is set to "1", A/D0 and A/D1 start conversions simultaneously. When read, its content is indeterminate. 0 0 : Selects ADTRG 0 1 : Selects a timer B2 interrupt request of the three-phase motor control timer functions (after ICTB2 counter completes counting) 1 0 : Selects the intelligent I/O group 2 channel 1 interrupt 1 1 : Do not set to this value NOTES: 1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Do not set the APS1 and APS0 bits to "1" while either A/D0 or A/D1 is operating. 3. The PST bit is enabled when the TRG bit in the AD0CON0 register is set to "0" (software trigger). Do not set the PST bit to "1" when the TRG bit is set to "1" (external trigger). 4. Set both A/D0 and A/D1 to the same setting. 5. If the ADS bit is set to "1", do not select single sweep mode or repeat sweep mode as the A/D operation mode. b7 b6 b5 b4 b3 b2 b1 b0 000 Figure 17.4 AD0CON2 Register, AD00 to AD07 Registers Function A/D0 Register i (i =0 to 7) Symbol Address After Reset AD00 to AD02 038116 - 038016, 038316 - 038216, 038516 - 038416 Indeterminate AD03 to AD05 038716 - 038616, 038916 - 038816, 038B16 - 038A16 Indeterminate AD06 to AD07 038D16 - 038C16, 038F16 - 038E16 Indeterminate RW RO RO 8 low-order bits in an A/D conversion result Nothing is assigned. When write, set to "0". When read, its content is indeterminate. In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its contents is indeterminate. b7 b0 b15 b8 |
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