M32C83T datasheet(272/527 Pages) RENESAS

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Page 249

21. Intelligent I/O

)

(

Figures 21.1 to 21.4 show block diagram of the intelligent I/O groups 0 to 3.

Figure 21.1 Intelligent I/O Group 0 Block Diagram

Reception

G0TM0, G0PO0

G0TM1, G0PO1

G0TM2, G0PO2

G0TM3, G0PO3

G0TM4, G0PO4

G0TM5, G0PO5

G0TM6, G0PO6

G0TM7, G0PO7

Base timer

PWM

output

PWM

output

PWM

output

Group0 base timer reset

Request by matching the base timer with the G0PO0 register

Request from the INT pin

Request from the group1

Divider

by 2(n+1)

DIV4 to DIV0

fBT0

Edge

select

Digital

filter

Edge

select

Digital

filter

Gate

function

Gate

function

Edge

select

Digital

filter

Edge

select

Digital

filter

Edge

select

Digital

filter

Edge

select

Digital

filter

Edge

select

Digital

filter

Edge

select

Digital

filter

INPC00

BCK1 to BCK0

10 : fBT0

11 : f1

10 : fBT0

11 : f1

10 : fBT0

11 : f1

10 : fBT0

11 : f1

10 : fBT0

11 : f1

10 : fBT0

11 : f1

10 : fBT0

11 : f1

10 : fBT0

11 : f1

INPC01

/ ISCLK0

INPC02

/ ISRxD0

INPC03

INPC04

INPC05

INPC06

INPC07

BTS

BT0S

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

CTS1 to CTS0

Ch0 to ch7

interrupt request signal

OUTC00/ISTxD0

OUTC01/ISCLK0

OUTC04

OUTC05

Arbitration

Comparator

Special

interrupt

check

G0CMP3 register

Buffer

Shift

Prescaler

function

Prescaler

function

Start bit

generation circuit

Bit insert circuit

SOF

generation circuit

Stop bit

generation circuit

Transmit latch

Transmit data

generation circuit

G0TCRC

Data

selector

Clock wait

control

circuit

Transmit

buffer

Polarity

inverse

G0TO register

Transmit

buffer

G0RB register

Receive

buffer

Receive data

generation circuit

Start bit

check

Bit insert

check

Stop bit

check

G0RCRC

G0RI register

Receive

buffer

Polarity

inverse

Clock

selector

Clock

selector

Waveform generation match

signal for group1

(For cascaded connection)

Time measurement trigger

for the group1

(For cascaded connection)

Overflow of base timer bit 15

Base timer interrupt request(3)

HDLC data receive

interrupt request

Transmit interrupt request

(SIO0TR)

(3)

(G0TOR)

(3)

(SIO0RR)

(3)

(SRT0R)

(3)

(G0RIR)

(3)

HDLC data transmit

interrupt request

Receive interrupt request

Special communication

interrupt request

Transmission

(Note 1)

G0DR register

(Receive data register)

Two-phase

pulse signal

is applied

G0TB register

(Transmit buffer register)

ch0

ch3

ch2

ch1

ch3

External clock

Transmit

operation clock

Receive operation clock

External clock

111

000 to 010

111

000 to 010

MOD2 to MOD0

Data

selector

TXSL

OPOL

RXSL

IPOL

DIV4 to DIV0 bits, BCK1 to BCK0 bits : Bits in the G0BCR0 register

BTS : Bit in the G0BCR1 register

BT0S : Bit in BTSR register

CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G0TMCRj register (j = 0 to 7)

MOD2 to MOD0 : Bits in the G0POCRj register

TXSL, RXSL : Bits in the G0EMR register

OPOL, IPOL : Bits in the G0CR register

NOTES:

1. These pins are not connected to external pins in the 100-pin package.

2. Each register enters a reset state after the G0BCR0 register supplies the

clock.

3. See Figure 10.14.

Reset

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