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M32C83T Datasheet(PDF) 273 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 273 Page - Renesas Technology Corp |
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273 / 527 page  Page 250 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 21. Intelligent I/O ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Figure 21.2 Intelligent I/O Group 1 Block Diagram Reception Transmission G1TM0, G1PO0 register G1TM1, G1PO1 register G1TM2, G1PO2 register G1TM3, G1PO3 register G1TM4, G1PO4 register G1TM5, G1PO5 register G1TM6, G1PO6 register G1TM7, G1PO7 register PWM output PWM output PWM output PWM output Group1 base timer reset Divider by 2(n+1) Edge select Digital filter Gate function Edge select Digital filter Gate function Edge select Digital filter INPC11 / ISCLK1 INPC16 INPC17 DIV4 to DIV0 GT GT PR PR CAS Ch0 to ch7 interrupt request signal OUTC10/ISTxD1/ BE1OUT OUTC11/ISCLK1 OUTC14 OUTC15 Arbitration Special interrupt check buffer register Shift register Prescaler function Prescaler function Start bit generation circuit Bit insert circuit SOF generation circuit Stop bit generation circuit Transmit latch Transmit data generation circuit Clock wait control circuit Transmit register Transmit buffer Polarity inverse Transmit register Transmit buffer Receive register Receive buffer Receive data generation circuit Start bit check Bit insert check Stop bit check G1RI register Receive register Receive buffer OUTC16 OUTC17 OUTC12 OUTC13 Waveform generation match signal from the group 0 (For cascaded connection) Time measurement trigger from the group 0 (For cascaded connection) HDLC data receive interrupt request Transmit interrupt request Receive interrupt request Special communication interrupt request Comparator Comparator Comparator Comparator (Note 1) (Note 2) (Note 2) G1CMP3 register G1CMP3 register G1CMP3 register G1CMP3 register G1RB register G1TO register G1TB register (Transmit buffer register) G1DR register (Receive data register) Base timer fBT1 overflow of bit 15 in the group0 base timer Edge select Digital filter INPC12 / ISRxD1 f1 Two-phase pulse signal is applied G1TCRC register G1RCRC register 111 000 to 010 000 to 010 MOD2 to MOD0 111 MOD2 to MOD0 Data selector TXSL OPOL 1 0 Data selector RXSL IPOL 1 0 Polarity inverse Clock selector Clock selector ch0 ch3 ch2 ch1 ch3 External clock Transmit operation clock Receive operation clock External clock DIV4 to DIV0, BCK1 to BCK0 : Bits in the G1BCR0 register CAS, BTS : Bits in the G1BCR1 register BT1S : Bit in the BTSR register CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj register (j = 0 to 7) MOD2 to MOD0 : Bits in the G1POCRj register TXSL, RXSL : Bits in the G1EMR register Request from the INT pin Request from the group0 BTS BT1S Request by matching the base timer with the G1PO0 register NOTES: 1. The G1TM0 register can be used in a 32-bit cascaded connection only. 2. These pins are not connected to external pins in the 100-pin package. 3. Each register is in a reset state after the G1BCR0 register supplies the clock. 4. See Figure 10.14. HDLC data transmit interrupt request (SIO1TR) (4) (G1TOR) (4) (G1RIR) (4) (SIO1RR) (4) (SRT1R) (4) Overflow of bit 15 in the base timer Base timer interrupt request (BT1R) (4) BCK1 to BCK0 11 10 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 CTS1 to CTS0 CTS1 to CTS0 00 DF1 to DF0 00 DF1 to DF0 00 DF1 to DF0 00 0 0 1 0 1 0 1 1 DF1 to DF0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CTS1 to CTS0 CTS1 to CTS0 |
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