M32C83T datasheet(277/527 Pages) RENESAS

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Page 254

21. Intelligent I/O

)

(

Figure 21.6 G0BCR1 and G1BCR1 Registers

Group i Base Timer Control Register 1 (i=0,1)

Symbol

Address

After Reset

G0BCR1, G1BCR1

00E316, 012316

0016

Bit Name

Function

Bit

Symbol

RST0

RST1

RST2

(b3)

Base Timer Reset

Cause Select Bit 0

Base Timer

Start Bit(5, 6)

BTS

UD0

CAS

UD1

Base Timer Reset

Cause Select Bit 1

Base Timer Reset

Cause Select Bit 2

Counter Increment/

Decrement Control Bit

0: Base timer is reset

1: Base timer starts counting

: Counter increment mode

: Counter increment/decrement mode

: Two-phase pulse signal processing

mode(7)

: Do not set to this value

Groups 0 and 1

Cascaded Connection

Function Select Bit

0: 16-bit time measurement or

waveform generation function

1: 32-bit time measurement or

waveform generation function(4)

Reserved Bit

Set to "0"

NOTES:

1. In group 0, the base timer is reset by synchronizing with the group 1 base timer reset. In group 1,

the base timer is reset by synchronizing with the group 0 base timer reset.

2. The base timer is reset two fBTi clock cycles after the base timer matches the value set in the GiPO0

value of the GiPOj register (j=1 to7) for the waveform generation function and communication

function must be set to a smaller value than that of the GiPO0 register.

3. In group 0, the base timer is reset when "L" is applied to the INT0 pin. In group 1, the base timer is

reset when "L" is applied to the INT1 pin.

4. When the CAS bit is set to "1" (32-bit time measurement, waveform generation function), set the

G0BCR1 register to "8116" and the G1BCR1 register to "1000 0XX02".

5. When starting the group 0 or 1 base timer separately, set the BTS bit to "1" after the BTkS bit (k=0 to

1) in the BTSR register is set to "0".

6. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the

BTS bit to "0".

7. In two-phase pulse signal processing mode, the base timer is not reset, even when the RST1 bit is

set to "1", if the counter is decremented two clock cycles after the base timer matches the value set

in the GiPO0 register

0: The base timer is not reset by

synchronizing with the base timer reset

1: The base timer is reset by synchronizing

with the base timer reset(1)

0: The base timer is not reset by

matching with the GiPO0 register

1: The base timer is reset by matching

with the GiPO0 register(2)

0: The base timer is not reset by

applying "L" to the INTi pin

1: The base timer is reset by applying

"L" to the INTi pin(3)

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