M32C83T datasheet(278/527 Pages) RENESAS

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Page 255

21. Intelligent I/O

)

(

Group 2 Base Timer Control Register 1

Symbol

Address

After Reset

G2BCR1

016316

0016

Bit Name

Function

Bit

Symbol

NOTES:

1. The base timer is reset two fBT2 clock cycles after the base timer matches the value set in the G2PO0

value of the G2POi register (i=1 to7), for the waveform generation function and communication

function, must be set to a smaller value than that of the G2PO0 register.

2. The PRP bit is valid when the RTP bit in the G2POCRi register is set to "1" (not used)

3. When starting the group 2 base timer, set the BTS bit to "1" after the BT2S bit in the BTSR register is

set to "0".

4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the

BTS bit to "0".

RST0

RST1

RST2

Base Timer

Reset Cause

Select Bit 0

Base Timer

Start Bit(3, 4)

BTS

(b3)

(b6 - b5)

Base Timer

Reset Cause

Select Bit 1

Base Timer

Reset Cause

Select Bit 2

Set to "0"

0 : Base timer is reset

1 : Base timer starts counting

Parallel Real-Time

Port Function

Select Bit(2)

PRP

0 : RTP output mode

1 : Parallel RTP output mode

Reserved Bit

Set to "0"

0 : The base timer is not reset by matching

with the G2PO0 register

1 : The base timer is reset by matching with

the G2PO0 register(1)

0 : The base timer is not reset by a reset

request from the communication function

1 : The base timer is reset by a reset request

from the communication function

0 : The base timer is not reset by synchronizing

with the group 1 base timer reset

1 : The base timer is reset by synchronizing

with the group 1 base timer reset

Figure 21.7 G2BCR1 Register

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