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M32C83T Datasheet(PDF) 279 Page - Renesas Technology Corp

Part # M32C83T
Description  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T Datasheet(HTML) 279 Page - Renesas Technology Corp

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Group 3 Base Timer Control Register 1
Symbol
Address
After Reset
G3BCR1
01A316
0016
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Function
Bit
Symbol
NOTES:
1. The base timer is reset after two fBT3 clock cycles after the base timer matches the value set in the
G3PO0 register. (See Figure 21.13 for details on the G3PO0 register.) When the RST1 bit is set to
"1", the value of the G3POi register (i=1 to7), for the waveform generation function and communication
function, must be set to a smaller value than that of the G2PO0 register.
2. The PRP bit is valid when the RTP bit in the G3POCRi register is set to "1" (not used)
3. When starting the group 3 base timer, set the BTS bit to "1" after the BT3S bit in the BTSR register is
set to "0".
4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS
bit to "0".
0 : The base timer is not reset by matching
with the G3PO0 register
1 : The base timer is reset by matching with
the G3PO0 register(1)
0 : The base timer is not reset by a reset
request from the communication function
1 : The base timer is reset by a reset request
from the communication function
RST0
RST1
Base Timer
Reset Cause
Select Bit 0
Base Timer
Start Bit(3, 4)
BTS
Base Timer
Reset Cause
Select Bit 1
Base Timer
Reset Cause
Select Bit 2
Set to "0"
0 : Base timer is reset
1 : Base timer starts counting
Parallel Real-Time
Port Function
Select Bit(2)
PRP
0 : RTP output mode
1 : Parallel RTP output mode
RST2
(b3)
(b6 - b5)
Reserved Bit
Reserved Bit
Set to "0"
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0 : The base timer is not reset by synchronizing
with the group 2 base timer reset
1 : The base timer is reset by synchronizing
with the group 2 base timer reset
Figure 21.8 G3BCR1 Register



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