M32C83T datasheet(276/527 Pages) RENESAS

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Page 253

21. Intelligent I/O

)

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Figures 21.5 to 21.15 show registers associated with the intelligent I/O base timer, the time measurement

function and waveform generation function. (For registers associated with the communication function, see

Figures 21.32 to 21.38, Figures 21.42 to 21.45, Figures 21.47 to 21.49.)

Figure 21.5 G0BT to G3BT Register and G0BCR0 to G3BCR0 Register

Group i Base Timer Register (i=0 to 3)(2)

Symbol

Address

After Reset

G0BT,G1BT

00E116 - 00E016, 012116 - 012016

Indeterminate

G2BT,G3BT

016116 - 016016, 01A116 - 01A016

Indeterminate

Function

Setting Range

000016 to FFFF16

b15

NOTES:

1. Each base timer stops only when the BCK1 to BCK0 bits in the GiBCR0 register are set to "002" (clock

stopped). The base timer counts when the BCK1 to BCK0 bits are set to a value other than "002".

When the BTiS bit in the BTSR register and the BTS bit in the GiBCR1 register are set to "0", the base

timer is reset continually, remaining set to "000016". This, in effect, places the base timer in a "no

counting" state. When either BTiS bit or BTS bit is set to "1", this state is cleared and counting starts.

2. The GiBT register reflects the value of the base timer with a delay of one half fBTi cycle.

When the base timer is counting:

When read, the value of the counter can be read.

When write, the counter starts counting from the

value written. When the base timer is reset, the

GiBT register is set to "000016"(1).

When the base timer is reset:

The GiBT register is set to "000016" but the

value is indeterminate. No value is written(1).

Group i Base Timer Control Register 0 (i=0 to 3)(1)

Symbol

Address

After Reset

G0BCR0 to G3BCR0

00E216, 012216, 016216, 01A216

0016

Bit Name

Function

Bit

Symbol

: Clock stops

: Do not set to this value

: Two-phase pulse signal is applied(2)

: f1

BCK0

BCK1

DIV0

Count Source

Select Bit

DIV1

Count Source

Divide Ratio

Select Bit

DIV2

DIV3

Base Timer

Interrupt Select Bit

0 : Bit 15 overflows

1 : Bit 14 overflows

DIV4

If setting value is n (n = 0 to 31),

count source is divided by 2(n + 1).

No division if n=31.

(n=0) 0 0 0 0 0 : Divide-by-2

(n=1) 0 0 0 0 1 : Divide-by-4

(n=2) 0 0 0 1 0 : Divide-by-6

(n=30) 1 1 1 1 0 : Divide-by-62

(n=31) 1 1 1 1 1 : No division

b6 b5 b4 b3 b2

NOTES:

1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement, waveform gene-

ration function), set the G0BCR0 register and G1BCR0 register to the same value.

2. This setting can be used only when the UD1 to UD0 bits in the GjBCR1 register (j=0, 1) of group 0

or 1 are set to "102" (two-phase signal processing mode). Do not set the BCK1 to BCK0 bits to

"102" in other modes or in group 2 or 3.

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