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M32C83T Datasheet(PDF) 274 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 274 Page - Renesas Technology Corp |
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274 / 527 page  Page 251 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 21. Intelligent I/O ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M PWM output control G2PO0 register G2PO1 register G2PO2 register G2PO3 register G2PO4 register G2PO5 register G2PO6 register G2PO7 register Base timer Group2 base timer reset Request from the communication function Request from the group1 Divider by 2(n+1) fBT2 BT2S BTS DIV4 to DIV0 Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM PWM output control PWM output control OUTC20 /ISTxD2/IEOUT PWM output control OUTC21 /ISCLK2 OUTC22 OUTC23 OUTC24 OUTC25 OUTC26 OUTC27 OPOL Waveform generation interrupt request Clock selector Clock synchronous serial I/O mode receive interrupt request Clock synchronous serial I/O mode transmit interrupt request Polarity inverse Receive register Output control function IE start bit interrupt request Real time port output value Digital filter IEIN /ISRxD2 ISCLK2 Bit counter Transmit register G2TB register Transmit parity calculation Polarity inverse Transmit latch Arbitration lost detection Byte counter IE, serial I/O interrupt control IE receive interrupt request IE transmit interrupt request ACK calculation Receive parity calculation Start bit detection G2RB register ID detection ALL "F" detection Address detect function Statement length detect function (Note 1) (SIO2TR)(3) (IE0R to IE2R)(3) (IE0R to IE2R)(3) (IE0R to IE2R)(3) PO2jR(3) (SIO2RR)(3) f1 Overflow of bit 15 in the base timer Base timer interrupt request BT2R (3) BCK1 to BCK0 11 0 1 DF IPOL 111 000 to 010, 100 MOD2 to MOD0 111 000 to 010, 100 MOD2 to MOD0 DIV4 to DIV0, BCK1 to BCK0 : Bits in the G2BCR0 register BTS : Bit in the G2BCR1 register BT2S : Bit in the BTSR register OPOL, IPOL : Bits in the G2CR register DF : Bit in the IECR register MOD2 to MOD0 : Bits in the G2POCRj register (j = 0 to 7) NOTES: 1. In the 100-pin package, these pins are not connected to external pins. 2. Each register enters a reset state after the G2BCR0 register supplies the clock. 3. See Figure 10.14. Request by matching the base timer with the G2PO0 register Figure 21.3 Intelligent I/O Group 2 Block Diagram |
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