M32C83T datasheet(288/527 Pages) RENESAS

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Page 265

21. Intelligent I/O (Base Timer)

)

(

Table 21.2 Base Timer Specifications (Continued)

Item

Specification

Selectable Function

• Two-phase pulse processing mode (Group 0 and 1)

Two-phase pulse signals from P76 and P77 pins in group 0, and P80

and P81 pins in group 1 are counted (See Figure 21.20)

Figure 21.16 Base Timer Block Diagram

Table 21.3 Base Timer Associated Register Settings

(for Time Measurement Function, Waveform Generation Function, and Communication Function)

Bit

Function

G2BCR0

Supplies operation clock to the BTSR register. Set to "0111 11112".

BTSR

Set to "0000 00002"

GiBCR0

BCK1 to BCK0

Select count source

DIV4 to DIV0

Select divide ratio of count source

Selects the base timer interrupt

GiBCR1

RST2 to RST1

Select factors for a base timer reset

BTS

Used to start the base timer independently

UD1 to UD0

Select how to count (Group 0 and 1)

CAS

Selects cascaded connection (Group 0 and 1)

GiBT

Read or write base timer value

Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register).

GiPOCR0

MOD2 to MOD0

Set to "0002" (single-phase waveform output mode)

GiPO0

Set reset cycle

GiFS

FSC0

Set to "0" (waveform generation function)

GiFE

IFE0

Set to "1" (channel operation start)

i : Bit configurations and functions vary with each group

The timer increments

counter on all edge

The timer decrements

counter on all deges

P76, P80

P77, P81

Divider

by 2(n+1)

RST0

RST1

RST2

Other base timer reset

Matching with the GiPO0 register

Apply "L" to the INTi pin (Group0,1)

Base timer

b14 b15

Base timer

interrupt request

BCK1 to BCK0

BTiS bit in BTSR register

BTS bit in GiBCR1 register

Request from communication

function (Group2,3)

Apply two-phase

pulse signal (

Group0,1)

(See the BTiR bit in Figure 10.14)

Overflow signal

Base timer reset

fBTi

NOTES:

1. Divider is reset when both BTiS bit and BTS bit are set to "0".

i = 0 to 3

BCK1 to BCK0, IT : Bits in the GiBCR0 register

RST2 to RST0 : Bits in the GiBCR1 register

(1)

b0 to b13

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