M32C83T datasheet(290/527 Pages) RENESAS

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Page 267

21. Intelligent I/O (Base Timer)

)

(

Figure 21.19 Counter Increment/ Decrement Mode (Group 0 and 1)

b15 overflow signal

BTkR bit in IIOjIR register

"1"

"0"

"1"

"0"

Write "0" by program

if setting to "0"

(1) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "0" (bit 15 in the base timer overflows)

b14 overflow signal

BTkR bit in IIOjIR register

"1"

"0"

"1"

"0"

Write "0" by program

if setting to "0"

(2) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "1" (bit 14 in the base timer overflows)

FFFF16

800016

Base Timer i

000016

400016

C00016

FFFF16

800016

Base Timer i

j=4, 7, 8, 11; k=0 to 3

The above applies under the following conditions:

• The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).

• The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).

j=4, 7, 8, 11; k=0 to 3

The above applies under the following conditions:

• The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).

• The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).

(3) When the RST1 bit in the GiBCR1 register (i= 0 to 1) is set to "1" (the base timer is reset by matching with the GiPO0 register)

800016

000016

800216

j=4, 7, 8, 11; k=0 to 3

The above applies under the following conditions:

• Value of GiPO0 register: "800016"

• The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode).

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