M32C83T datasheet(287/527 Pages) RENESAS

287 / 527 page

Page 264

21. Intelligent I/O (Base Timer)

)

(

21.1 Base Timer

The base timer is a free-running counter that counts an internally generated count source.

Table 21.2 lists specifications of the base timer. Figures 21.5 to 21.9 show registers associated with the

base timer. Figure 21.16 shows a block diagram of the base timer. Figure 21.17 shows an example of a

cascaded connection. Figure 21.18 shows an example of the base timer in counter increment mode. Figure

21.19 shows an example of the base timer in counter increment/decrement mode. Figure 21.20 shows an

example of two-phase pulse signal processing mode.

Table 21.2 Base Timer Specifications

Item

Specification

Count Source (fBTi) (i=0 to 3)

f1 divided by

2(n+1) (Group 0 to 3),

two-phase pulse input divided by

2(n+1) (Group 0 and 1)

n: determined by the DIV4 to DIV0 bits in the GiBCR0 register

n=0 to 31; however no division when n=31

Counting Operation

The base timer increments the counter

The base timer increments/decrements the counter

Two-phase pulse signal processing

Counter Start Condition

• When starting the base timer of each group separately, set the BTS bit in

the GiBCR1 register to "1" (base timer starts counting)

• When starting the base timer of multiple groups simultaneously, set the

BTiS bit in the BTSR register to "1" (base timer starts counting)

Counter Stop Condition

Set the BTiS bit in the BTSR register to "0" (base timer reset) and the BTS

bit in the GiBCR1 register to "0" (base timer reset)

Base Timer Reset Condition

• Synchronized with the base timer reset in different groups:

Group0 : synchronized with group 1 base timer reset

Group1 : synchronized with group 0 base timer reset

Group2 : synchronized with group 1 base timer reset

Group3 : synchronized with group 2 base timer reset

• Matching values in the base timer and GiPO0 register

• "L" signal applied to the external interrupt pin

________

Group 0 : INT0 pin

________

Group 1 : INT1 pin

• Reset request from communication function (Group 2 and 3)

Value when the Base Timer is Reset

"000016"

Interrupt Request

The BTiR bit in the interrupt request register is set to "1" (interrupt requested)

when bit 14 or bit 15 in the base timer overflows (See Figure 10.14.)

Read from Base Timer

• The GiBT register indicates counter value while the base timer is running

• The GiBT register is indeterminate when the base timer is reset

Write to Base Timer

When a value is written while the base timer is running, the counter

immediately starts counting from this value. No value can be written while

the base timer is reset.

Selectable Function

• Cascaded connection (Group 0 and 1)

Group 1 base timer is incremented every time bit 15 in the group 0 base

timer overflows (See Figure 21.17)

• Counter increment/decrement mode (Group 0 and 1)

The base timer starts when the BTS bit or the BTiS bit is set to "1". After

incrementing to "FFFF16", the counter is then decremented back to

"000016". If the RST1 bit in the GiBCR1 register is set to "1" (the base timer

is reset by matching with the GiPO0 register), the counter decrements after

the base timer matches the GiPO0 register. The base timer increments the

counter again when the counter becomes "000016." (See Figure 21.19.)

M32C83T Datasheet(PDF) 287 Page - Renesas Technology Corp

M32C83T Datasheet(HTML) 287 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL