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M32C83T Datasheet(PDF) 289 Page - Renesas Technology Corp

Part # M32C83T
Description  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T Datasheet(HTML) 289 Page - Renesas Technology Corp

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Page 266
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21. Intelligent I/O (Base Timer)
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Figure 21.17 Cascaded Connection
f1
fBT1
Bit 15 overflow in
the group0 base timer
Two-phase pulse
signal is applied
Waveform generation
match signal
Request from the INT pin
Request by matching the base timer
with the G1PO0 register
Request from group0
BT0S, BT1S : Bits in the BTSR register
BTS, CAS : Bits in the GiBCR1 register (i=0,1)
BCK1 to BCK0 : Bits in the GiBCR0 register (i = 0,1)
j=0 to 7, k=1,2,6,7
BT0S
BTS
BCK1 to BCK0
10
11
BT1S
BTS
CAS
CAS
1
0
1
0
CAS
1
0
Divider
by 2(n+1)
Group0
base timer
G0TMj register
G0POj register
Group1
base timer
G1TMj register
G1POj register
Request from the INT pin
Request by matching the base timer
with the G0PO0 register
Request from group1
INPC1k triggered by
the time measurement
INPC0j triggered by
the time measurement
Figure 21.18 Counter Increment Mode (Group 0 and 1)
j=4,7,8,11 k=0 to 3
The above applies under the following conditions:
• The RST1 bit in the GiBCR1 register is set to "0" (the base timer is not reset by matching the base
timer with the GiPO0 register)
• The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode)
j=4,7,8,11 k=0 to 3
The above applies under the following conditions:
• The RST1 bit in the GiBCR1 register is set to "0" (the base timer is not reset by matching the base
timer with the GiPO0 register)
• The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode)
BTkR bit in IIOjIR register
BTkR bit in IIOjIR register
Base Timer i
Base Timer i
b14 overflow signal
b15 overflow signal
Write "0" by program
if setting to "0"
FFFF16
800016
000016
(1)
The IT in the GiBCR0 register (i=0,1) is set to "0" (bit 15 in the base timer overflows)
(2)
The IT in the GiBCR0 register (i=0,1) is set to "1" (bit 14 in the base timer overflows)
"1"
"0"
"0"
"1"
FFFF16
800016
000016
"1"
"0"
"0"
"1"
400016
C00016
Write "0" by program
if setting to "0"



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