HD6412321 datasheet(58/1302 Pages) RENESAS

58 / 1302 page

Section 1 Overview

Rev.6.00 Sep. 27, 2007 Page 28 of 1268

REJ09B0220-0600

Pin No.

Type

Symbol

TFP-120

FP-128B

I/O

Name and Function

Bus control

CAS*4

116

126

Output Upper column address strobe/

column address strobe: The 2-CAS

type DRAM upper column address

strobe signal.

LCAS*4

Output Lower column address strobe: The

2-CAS type DRAM lower column

address strobe signal.

WAIT

86, 92

94, 102

Input

Wait: Requests insertion of a wait

state in the bus cycle when

accessing external 3-state access

space.

DMA controller

(DMAC) *

DREQ

62, 60

70, 66

Input

DMA request 1 and 0: These pins

request DMAC activation.

TEND

63, 61

71, 69

Output DMA transfer end 1 and 0: These

pins indicate the end of DMAC data

transfer.

DACK

111, 112

121, 122

Output DMA transfer acknowledge 1 and

0: These are the DMAC single

address transfer acknowledge pins.

16-bit timer

pulse unit

(TPU)

TCLKD to

TCLKA

105, 107,

109, 110

115, 117,

119, 120

Input

Clock input D to A: These pins input

an external clock.

TIOCA0,

TIOCB0,

TIOCC0,

TIOCD0

112 to

109

122 to

119

I/O

Input capture/output compare

match A0 to D0: The TGR0A to

TGR0D input capture input or output

compare output, or PWM output pins.

TIOCA1,

TIOCB1

108, 107

118, 117

I/O

Input capture/output compare

match A1 and B1: The TGR1A and

TGR1B input capture input or output

compare output, or PWM output pins.

TIOCA2,

TIOCB2

106, 105

116, 115

I/O

Input capture/output compare

match A2 and B2: The TGR2A and

TGR2B input capture input or output

compare output, or PWM output pins.

TIOCA3,

TIOCB3,

TIOCC3,

TIOCD3

71 to 68

79 to 76

I/O

Input capture/output compare

match A3 to D3: The TGR3A to

TGR3D input capture input or output

compare output, or PWM output pins.

HD6412321 Datasheet(PDF) 58 Page - Renesas Technology Corp

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