HD6412321 datasheet(28/1302 Pages) RENESAS

28 / 1302 page

Rev.6.00 Sep. 27, 2007 Page xxviii of xxx

REJ09B0220-0600

Section 20 Clock Pulse Generator .....................................................................911

20.1

Overview........................................................................................................................... 911

20.1.1 Block Diagram ..................................................................................................... 911

20.1.2 Register Configuration......................................................................................... 912

20.2

Register Descriptions ........................................................................................................ 912

20.2.1 System Clock Control Register (SCKCR) ........................................................... 912

20.3

Oscillator........................................................................................................................... 914

20.3.1 Connecting a Crystal Resonator........................................................................... 914

20.3.2 External Clock Input ............................................................................................ 916

20.4

Duty Adjustment Circuit ................................................................................................... 918

20.5

Medium-Speed Clock Divider .......................................................................................... 918

20.6

Bus Master Clock Selection Circuit .................................................................................. 918

Section 21 Power-Down Modes ........................................................................919

21.1

Overview........................................................................................................................... 919

21.1.1 Register Configuration......................................................................................... 920

21.2

Register Descriptions ........................................................................................................ 921

21.2.1 Standby Control Register (SBYCR) .................................................................... 921

21.2.2 System Clock Control Register (SCKCR) ........................................................... 923

21.2.3 Module Stop Control Register (MSTPCR) .......................................................... 925

21.3

Medium-Speed Mode........................................................................................................ 925

21.4

Sleep Mode ....................................................................................................................... 926

21.5

Module Stop Mode............................................................................................................ 927

21.5.1 Module Stop Mode .............................................................................................. 927

21.5.2 Usage Notes ......................................................................................................... 928

21.6

Software Standby Mode.................................................................................................... 929

21.6.1 Software Standby Mode....................................................................................... 929

21.6.2 Clearing Software Standby Mode ........................................................................ 929

21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 930

21.6.4 Software Standby Mode Application Example .................................................... 930

21.6.5 Usage Notes ......................................................................................................... 931

21.7

Hardware Standby Mode .................................................................................................. 932

21.7.1 Hardware Standby Mode ..................................................................................... 932

21.7.2 Hardware Standby Mode Timing......................................................................... 932

21.8

φ Clock Output Disabling Function ..................................................................................933

Section 22 Electrical Characteristics .................................................................935

22.1

Electrical Characteristics of Mask ROM Version (H8S/2328, H8S/2327, H8S/2323)

and ROMless Version (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320) ........................ 935

22.1.1 Absolute Maximum Ratings ................................................................................ 935

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