R/C

BUSY

MODE

Parallel

Data Bus

BYTE

Previous

High Byte Valid

Hi-Z

Previous High

Byte Valid

Previous Low

Byte Valid

Not Valid

High Byte

Valid

Low Byte

Valid

Hi-Z

High Byte

Valid

Acquire

Convert

Acquire

Convert

Hi-Z State

High Byte

Hi-Z State

Low Byte

Hi-Z State

R/C

BUSY

CS

Data Bus

BYTE

ADS8517

Parallel Output (After a Conversion)

After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid

data from conversion N are available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the

data. Refer to Table 5, Figure 30, and Figure 31 for timing specifications.

Figure 30. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High)

Figure 31. CS to Control Conversion and Read Timing With Parallel Outputs

16

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