ADS8517 AS AN SPI SLAVE DEVICE (INT/EXT TIED HIGH)

Microcontroller

SPIMaster

CPOL=0(inactiveSCLKisLOW)

CPHA=1(datavalidonSCLKfallingedge)

NOTE:

ADS8517

SPISlave

TOUT

INT

MOSI

SCLK

R/C

BUSY

SDATA

DATACLK

CS

EXT/INT

V

S

BYTE

8-BIT SPI INTERFACE

ADS8517

Figure 45 shows another interface between the ADS8517 and an SPI-equipped microcontroller or DSP in which

the host processor acts as an SPI master device.

Figure 45. ADS8517 as SPI Slave

In this configuration, the data transfer from the ADS8517 is triggered by the rising edge of the serial data clock

provided by the SPI master. The SPI interface should be configured to read valid SDATA on the falling edge of

SCLK. When a minimum of 17 SCLKs are provided to the ADS8517, data can be strobed to the host processor

When using an external interrupt to facilitate serial data transfers, as shown in Figure 45, there are two options

for the configuration of the interrupt service routine (ISR): falling-edge-triggered or rising-edge-triggered.

A falling-edge-triggered transfer would initiate an SPI transfer after the falling edge of BUSY, providing the host

controller with the previous conversion results, while the current conversion cycle is underway. The timing for this

type of interface is described in detail in Figure 36. Care must be taken to ensure the entire 16-bit conversion

result is retrieved from the ADS8517 before BUSY returns high to avoid the potential corruption of the current

conversion cycle.

A rising-edge-triggered transfer is the preferred method of obtaining the conversion results. This timing is

depicted in Figure 35. This method of obtaining data ensures that SCLK is static during the conversion cycle and

provides the host processor with current cycle conversion results.

For microcontrollers that only support 8-bit SPI transfers, it is recommended to configure the ADS8517 for SPI

slave operation, as depicted in Figure 45. With the microcontroller configured as the SPI master, two 8-bit

transfers are required to obtain full 16-bit conversion results from the ADS8517. The eight MSBs of the

conversion result are considered valid on the falling SCLK edges of the first transfer, with the remaining four

LSBs being valid on the first four falling SCLK edges in the second transfer.

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