HD6432142 datasheet(1169/1177 Pages) RENESAS

1169 / 1177 page

Appendix D Pin States

Rev. 4.00 Sep 27, 2006 page 1125 of 1130

REJ09B0327-0400

Port Name

Pin Name

MCU Operating

Mode

Reset

Hardware

Standby

Mode

Software

Standby

Mode

Watch

Mode

Sleep

Mode

Sub-

sleep

Mode

Subactive

Mode

Program

Execution

State

Clock

output

EXCL

input

EXCL

input

EXCL input

2, 3 (EXPE = 1)

Port 96

EXCL

2, 3 (EXPE = 0)

[DDR = 1]

[DDR = 0]

[DDR = 1]

clock

output

[DDR = 0]

Clock output/

EXCL input/

input port

2, 3 (EXPE = 1)

AS, HWR,

Port 95 to 93

AS, HWR,

2, 3 (EXPE = 0)

keep

I/O port

Port 92 to 91

keep

I/O port

2, 3 (EXPE = 1)

2, 3 (EXPE = 0)

H/keep

H/keep H/keep

H/keep

2, 3 (EXPE = 1)

LWR/

I/O port

LWR/

I/O port

Port 90

LWR

2, 3 (EXPE = 0)

keep

I/O port

keep*

I/O port

2, 3 (EXPE = 1)

A23 to A16/

I/O port

A23 to A16/

I/O port

Port A

A23 to A16

2, 3 (EXPE = 0)

I/O port

T/keep

Port B

D7 to D0

2, 3 (EXPE = 1)

D7 to D0/

I/O port

D7 to D0/

I/O port

2, 3 (EXPE = 0)

keep

I/O port

Legend:

High

Low

High-impedance state

keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, MOS input pull-

ups remain on).

Output ports maintain their previous state.

Depending on the pins, the on-chip supporting modules may be initialized and the I/O port

function determined by DDR and DR used.

DDR: Data direction register

Note:

In the case of address output, the last address accessed is retained.

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